NCV4299
http://onsemi.com
17
Setting the Delay Time
The delay time is set by the delay capacitor C
D
and the
charge current I
D
. The time is measured by the delay
capacitor voltage charging from the low level of V
D,sat
to the
higher level V
UD
. The time delay follows the equation:
t
d
+ [C
D
(V
UD
-V
D, sat
)]ńI
D
(eq. 2)
Example:
Using C
D
= 100 nF.
Use the typical value for V
D,sat
= 0.1 V.
Use the typical value for V
UD
= 1.8 V.
Use the typical value for Delay Charge Current I
D
= 6.5 mA.
t
d
+ [100nF(1.8-0.1V)]ń6.5mA + 26.2ms
(eq. 3)
When the output voltage V
Q
drops below the reset
threshold voltage V
RT
, the voltage on the delay capacitor V
D
starts to drop. The time it takes to drop below the lower
threshold voltage of V
LD
is the reset reaction time, t
RR
. This
time is typically 2.2 ms for a delay capacitor of 0.1 mF. The
reset reaction time can be estimated from the following
relationship:
t
RR
+ 22nsńnF C
D
(eq. 4)
Sense Input (SI)/Sense Output (SO) Voltage Monitor
An on-chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figures 39 and 40). The
typical threshold is 1.35 V on the SI Pin.
Signal Output
Figure 42 shows the SO Monitor waveforms as a result of
the circuits depicted in Figures 39 and 40. As the output
voltage V
Q
falls, the monitor threshold V
SI,LOW
is crossed.
This causes the voltage on the SO output to go low sending
a warning signal to the microprocessor that a reset signal may
occur in a short period of time. T
WA R NI N G
is the time the
microprocessor has to complete the function it is currently
working on and get ready for the reset shutdown signal.
t
PD
SO
LH
t
PD
SO
HL
t
t
Sense
Input
Voltage
V
SL,
High
V
SL,
Low
Sense
Output
High
Low
V
Q
S
I
V
SI,LOW
V
RO
S
O
T
WARNING
Figure 42. SO Warning Timing Waveform Figure 43. Sense Timing Diagram
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator is:
P
D(max)
+ [V
I(max)
-V
Q(min)
]I
Q(max)
) V
I(max)
Iq
(eq. 5)
where:
V
I(max)
is the maximum input voltage,
V
Q(min)
is the minimum output voltage,
I
Q(max)
is the maximum output current for the application,
and
I
q
is the quiescent current the regulator consumes at I
Q(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+ (150°C-T
A
)ńP
D
(eq. 6)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
's less than the calculated value in Equation 6 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required.
