NCP81063
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7
APPLICATIONS INFORMATION
The NCP81063 gate driver is a single−phase MOSFET
driver designed for driving N−channel MOSFETs in a
synchronous buck converter topology.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low−R
DS(on)
N−channel MOSFET. The
voltage supply for the low−side driver is internally
connected to the VCC and GND pins.
High−Side Driver
The high−side driver is designed to drive a floating
low−R
DS(on)
N−channel MOSFET. The gate voltage for the
high−side driver is developed by a bootstrap circuit
referenced to the SW pin.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor. When the NCP81063
is starting up, the SW pin is held at ground, allowing the
bootstrap capacitor to charge up to VCC through the
bootstrap diode. When the PWM input is driven high, the
high−side driver will turn on the high−side MOSFET using
the stored charge of the bootstrap capacitor. As the
high−side MOSFET turns on, the SW pin rises. When the
high−side MOSFET is fully turned on, SW will settle to
VIN and BST will settle to VIN + VCC (excluding parasitic
ringing).
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (C
BST
) and an integrated diode to provide current
to the high−side driver. A multi−layer ceramic capacitor
(MLCC) with a value greater than 100 nF should be used
for C
BST
.
Power Supply Decoupling
The NCP81063 can source and sink relatively large
currents to the gate pins of the MOSFETs. In order to
maintain a constant and stable supply voltage, a low−ESR
capacitor should be placed near the VCC and GND pins. A
MLCC between 1 mF and 4.7 mF is typically used.
Undervoltage Lockout
DRVH and DRVL are low until VCC reaches the VCC
UVLO threshold, typically 4.35 V. Once VCC reaches this
threshold, the PWM signal will control DRVH and DRVL.
There is a 200 mV hysteresis on VCC UVLO. There are
pull−down resistors on DRVH, DRVL and SW to prevent
the gates of the MOSFETs from accumulating enough
charge to turn on when the driver is powered off.
Bi−Directional EN Signal
The Enable pin (EN) is used to disable the DRVH and
DRVL outputs to prevent power transfer. When EN is
above the EN
HI
threshold, DRVH and DRVL change their
states according to the PWM input. A UVLO fault turns on
the internal MOSFET that pulls the EN pin towards ground.
By connecting EN to the DRON pin of a controller, the
controller is alerted when the driver encounters a fault
condition.
Three−State PWM Input
Switching PWM between logic−high and logic−low
states will allow the driver to operate in continuous
conduction mode as long as VCC is greater than the UVLO
threshold and EN is high. The threshold limits are specified
in the electrical characteristics table in this datasheet. Refer
to Figure 21 for the gate timing diagrams and Table 1 for
the EN/PWM logic table.
When PWM is set above PWM
HI
, DRVL will first turn
off after a propagation delay of tpdl
DRVL
. To ensure
non−overlap between DRVL and DRVH, there is a delay of
tpdh
DRVH
from the time DRVL falls to 1 V, before DRVH
is allowed to turn on.
When PWM falls below PWM
LO
, DRVH will first turn
off after a propagation delay of tpdl
DRVH
. To ensure
non−overlap between DRVH and DRVL, there is a delay of
tpdh
DRVL
from the time DRVH – SW falls to 1 V, before
DRVL is allowed to turn on.
When PWM enters the mid−state voltage range,
PWM
MID
, DRVL goes high after the non−overlap delay,
and stays high for the duration of the ZCD blanking timer
and an 80 ns de−bounce timer. Once these timers expire,
SW is monitored for zero current detection and pulls DRVL
low once zero current is detected.
Thermal Considerations
As power in the NCP81063 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient
temperature affect the rate of junction temperature rise for
the part. When the NCP81063 has good thermal
conductivity through the PCB, the junction temperature
will be relatively low with high power applications. The
maximum dissipation the NCP81063 can handle is given
by:
P
D(MAX)
+
ƪ
T
J(MAX)
* T
A
ƫ
R
qJA
(eq. 1)
Since T
J
is not recommended to exceed 150°C, the
NCP81063, soldered on to a 645 mm
2
copper area, using
1 oz. copper and FR4, can dissipate up to 2.3 W when the
ambient temperature (T
A
) is 25°C. The power dissipated by
the NCP81063 can be calculated from the following
equation:
P
D
+ VCC
ƪǒ
n
HS
Qg
HS
) n
LS
Qg
LS
Ǔ
f ) I
standby
ƫ
(eq. 2)
Where n
HS
and n
LS
are the number of high−side and
low−side FETs, respectively, Qg
HS
and Qg
LS
are the gate
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
