NB3N3020DTR2G Datasheet NB3N3020DTR2G, NB3N3020DTG | P1-P3

January, 2014 − Rev. 4

1 Publication Order Number:

NB3N3020/D

NB3N3020

3.3 V, LVPECL/LVCMOS

Clock Multiplier

Description

The NB3N3020 is a high precision, low phase noise selectable clock

multiplier. The device takes a 5 – 27 MHz fundamental mode parallel

resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source

and generates a differential LVPECL output and a single ended

LVCMOS/LVTTL output at a selectable clock output frequency which

is a multiple of the input clock frequency. Three tri−level (Low, Mid,

High) LVCMOS/LVTTL single ended select pins set one of 26

possible clock multipliers. The LVCMOS/LVTTL output enable

(OE1) tri−states the LVCMOS/LVTTL clock output (CLK1) when

low. When the LVTTL/LVCMOS output enable (OE2) is LOW,

LVPECL CLK2 is forced LOW and LVPECL CLK2

is forced HIGH.

This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin

package.

Features

• Selectable Clock Multiplier

• External Loop Filter is Not Required

• LVPECL Differential Output

• LVCMOS/ LVTTL Outputs

• RMS Period Jitter of 5 ps

• Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:

Offset Noise Power

100 Hz −95 dBc/Hz

1 kHz −107 dBc/Hz

10 kHz −112 dBc/Hz

100 kHz −117 dBc/Hz

1 MHz −117 dBc/Hz

10 MHz −134 dBc/Hz

• Operating Range 3.3 V ±10%

• Industrial Temperature Range −40°C to +85°C

• These are Pb−Free Devices

MARKING

DIAGRAM

TSSOP−16

DT SUFFIX

CASE 948F

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

NB3N

3020

ALYWG

(*Note: Microdot may be in either location)

(Top View)

PIN CONFIGURATION

OE2

VDD

CLK2

GND

VDD

CLK1

GND

VDD

X1/CLK

Sel2

Sel1

Sel0

OE1

GND

116

NB3N3020

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Phase

Detector

Loop Filter VCO

Clock

Buffer/

Crystal

Oscillator

Select Control Block

Pre

Sca

ler

LVCMOS/

LVPECL

Output

VDD

GND

OE2

OE1

CLK1

CLK2

Sel0 Sel1 Sel2

X1 /CLK

5−27 MHz Crystal

2 – 210 MHz Clock

Figure 1. NB3N3020 Simplified Logic Diagram

LVTTL

Output

CLK2

Table 1. PIN DESCRIPTION

Pin Name I/O Description

6 Sel0 Tri−Level Input Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2

for details.

5 Sel1 Tri−Level Input Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2

for details.

4 Sel2 Tri−Level Input Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2

for details.

1, 11, 15 V

Power Supply Positive supply voltage pins are connected to +3.3 V supply voltage.

2 X1/CLK Input Crystal or Clock input. Connect to 5 − 27 MHz crystal source or 2 – 210 MHz single−

ended clock. See Table 2.

3 X2 Input Crystal input. Connect to a 5 – 27 MHz crystal or leave unconnected for clock input. See

Table 2.

7 OE1 LVTTL/LVCMOS

Input

Output enable input that synchronously tri−states CLK1 output when low. Internal pull−up

resistor to V

16 OE2 LVTTL/LVCMOS

Input

Output enable input that when LOW synchronously controls LVPECL outputs by forcing

CLK2 LOW and CLK2

HIGH. Internal pull−up resistor to V

8, 9, 12 GND Power Supply Ground 0 V. These pins provide GND return path for the devices.

13 CLK2 LVPECL Output Inverted clock output. Clock frequency equals input frequency times multiplier.

14 CLK2 LVPECL Output Non−inverted clock output. Clock frequency equals input frequency times multiplier.

10 CLK1 LVTTL/ LVCMOS

Output

Clock Output. Clock frequency equals input frequency times multiplier.

NB3N3020

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Table 2. OUTPUT FREQUENCY CLOCK MULTIPLIER SELECT TABLE

Sel2 Sel1 Sel0 CLK1, CLK2, CLK2 Clock Input Range [MHz] Crystal Input Range [MHz]

L L L Low (Power Down) − −

L L M Input X 1 25 − 210 25 − 27

L L H Input X 4/3 (or 1 1/3) 15 −157.5 15 − 27

L M L Input X 1.5 10 − 140 10 − 27

L M M 1.6 25 – 131.25 25 − 27

L M H Input X 1.875 40 − 112 −

L H L Input X 2 25 − 105 25 − 27

L H M Input X 7/3 (or 2 1/3) 15 − 90 15 − 27

L H H Input X 2.4 25 – 87.5 25 − 27

M L L Input X 2.5 10 − 84 10 − 27

M L M Input X 8/3 (or 2 2/3) 15 − 78.75 15 − 27

M L H Input X 3 15 − 70 15 − 27

M M L Input X 3.125 40 – 67.20 −

M M M Input X 3.2 25 – 65.63 25 − 27

M M H Input X 10/3 (or 3 1/3) 15 − 63 15 − 27

M H L Input X 3.75 20 − 56 20 − 27

M H M Input X 4 2 – 52.5 5 − 25

M H H Input X 5 6 − 42 6 − 27

H L L Input X 6 5 − 35 5 − 27

H L M Input X 6.25 20 – 33.6 20 − 27

H L H Input X 19/3 (or 6 1/3) 15 – 33.16 15 – 27

H M L Input X 8 5 – 26.25 5 – 26.25

H M M Input X 25/3 (or 8 1/3) 15 – 25.2 15 – 25.2

H M H Input X 10 5 − 21 5 − 21

H H L Input X 12 5 – 17.5 5 – 17.5

H H M Input X 12.5 10 – 16.8 10 – 16.8

H H H Input X 16 5 − 13.125 5 – 13.125

L – Low, M – Mid, H − High

Recommended Crystal Parameters

Crystal Fundamental AT−Cut

Frequency 5 − 27 MHz

Load Capacitance 16 − 20 pF

Shunt Capacitance, C0 7 pF Max

Equivalent Series Resistance 35 W Max

Initial Accuracy at 25°C ±20 ppm

Temperature Stability ±30 ppm

Aging ±20 ppm

C0/C1 Ration 250 Max

Device Operation

The NB3N3020 is a Clock multiplier. The device can take

crystal or clock input and generates LVPECL and

LVCMOS/ LVTTL clock outputs which are multiples of the

input as determined by the tri−level select inputs [Sel0, Sel1,

Sel2].

Clock Multiplication

NB3N3020 is a clock multiplier with the clock multiplier

selected by the tri level select inputs [Sel0, Sel1, Sel2].

NB3N3020 has a LVTTL/LVCMOS output [CLK1] and a

LVPECL clock output [CLK2, CLK2

Output Enable

The device has an output enable [OE] which is used to

tri−state the outputs. OE1 controls the CLK1 clock output

where as OE2 controls the CLK2, CLK2

clock outputs.

When OE1or OE2 are disabled, the respective clock

output(s) are tri−stated. In this mode of operation, PLL is

still running, with the respective clock outputs tri−stated.

When the OE1 or OE2 are enabled, the clock outputs

P1-P3 P4-P6 P7-P9

NB3N3020DTR2G

Mfr. #:

Buy NB3N3020DTR2G

Manufacturer:

ON Semiconductor

Description:

Phase Locked Loops - PLL LVPECL CLK MULTIPLR 3.3V

Lifecycle:

New from this manufacturer.

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NB3N3020DTR2G

NB3N3020DTR2G

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