NB3N3020
http://onsemi.com
4
become active synchronous to the internal PLL output clock
and do not create any glitches or runt pulses during the
transition. In power down mode, the outputs are tri−stated
regardless of the state of the OE1, OE2.
The device has an output enable [OE1] which accepts
LVTTL/LVCMOS levels and when set LOW will disable
the LVTTL/LVCMOS level CLK1 to tri*state. Output
enable OE2 accepts LVTTL/LVCMOS levels to disable the
LVPECL level outputs by forcing CLK2 LOW and CLK2b
HIGH. When OE1 or OE2 are set LOW (Disabled), the PLL
remains running while the respective clock outputs are
disabled. When the OE1 or OE2 are set enabled (HIGH), the
clock outputs become active synchronous to the internal
PLL output clock and will not create any glitches or runt
pulses during the transition. Both OE1 and OE2 inputs have
pull−up resistors which default to VDD when floated open.
In power down mode, the outputs are tri*stated (zero
current) regardless of the state of the OE1, OE2.
Changing Clock Multiplier
The clock output frequency can be dynamically changed
using Sel0, Sel1, Sel2 pins. When the clock frequency is
changed, the clock outputs move from one frequency to
another and the PLL locks to the new frequency within a
settling time of 3 msec. There is no glitch during this
transition when the clock outputs are active {not tri−stated
by OE1, OE2}.
Crystal/ Clock Input
The device takes in a 5 – 27 MHz crystal input or 2 –
210 MHz clock input. Once powered up, the input frequency
is fixed and should not be changed dynamically. The input
cannot accept a spread spectrum clock and needs a fixed
frequency clock for device operation. The input frequencies
for clock and crystal input for specific multipliers are
determined by Table 3.
Power Up
When the NB3N3020 is powered up, it takes 10 msec for
the PLL’s to stabilize and lock to the desired frequency of
operation as selected by Sel0, Sel1, Sel2. During this time
period, there may be glitches in the clock outputs.
Power Down:
The device can be powered down when the Sel0, Sel1,
Sel2 pins are all connected to GND. In this mode of
operation, PLL is turned off and the device consumes less
than 5 mA of current. There may be a glitch in clock outputs
when the device is powering down. In power down mode,
the outputs are tri−stated regardless of the state of the OE1,
OE2.
In the cases where the application requires glitch−less
transitions, in order to avoid glitches it is recommended to
use synchronous OE signaling to mask glitches to the clock
outputs.
