1
FEBRUARY 2009
CMOS SyncFIFO
TM
64 x 36
IDT723611
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.
DSC-3024/3
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
©
FEATURES:
••
••
• Free-running CLKA and CLKB may be asynchronous or coincident
(permits simultaneous reading and writing of data on a single clock
edge)
••
••
• 64 x 36 storage capacity
••
••
• Synchronous data buffering from Port A to Port B
••
••
• Mailbox bypass register in each direction
••
••
• Programmable Almost-Full (AF) and Almost-Empty (AE) flags
••
••
• Microprocessor Interface Control Logic
••
••
• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
••
••
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
••
••
• Passive parity checking on each Port
••
••
• Parity Generation can be selected for each Port
••
••
• Supports clock frequencies up to 67MHz
••
••
• Fast access times of 10ns
••
••
• Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
••
••
• Industrial temperature range (–40
°°
°°
°C to +85
°°
°°
°C) is available
••
••
• Green parts available, see ordering information
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67MHz
and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers
data from Port A to Port B. The FIFO has flags to indicate empty and full conditions,
and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to
indicate when a selected number of words is stored in memory. Communication
between each port can take place through two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity
is checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
may be used in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
EF
AE
B
0
- B
35
FF
AF
FS
0
FS
1
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
Parity
Gen/Check
PGB
PEFB
36
RAM
ARRAY
64 x 36
3024 drw 01
PGA
PEFA
MBF2
