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IDT723611L15PQF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
7
IDT723611
CMOS SyncFIFO
TM
64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
CALCULATING POWER DISSIPATION
The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with CLKA and CLKB operating at
frequency fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were discon-
nected to normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be
calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT = VCC x ICC(f) +
Σ
(CL x VOH - VOL)
2
X fO)
where:
CL = output capacitance load
fO = switching frequency of an output
VOH = output high-level voltage
VOL = output low-level voltage
When no read or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.290 mA/MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
010203040506070
0
50
100
150
200
250
300
350
400
VCC = 5.0V
fdata = 1/2 fS
CL = 0 pF
80
VCC = 4.5V
VCC = 5.5V
3024 drw 04
TA = 25°C
Icc(f) Supply Current mA
fclock ⎯ Clock Frequency ⎯ MHz
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFO
TM
64 x 36
64 x 36
FEBRUARY 13, 2009
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURES
Commercial Com'l & Ind'l
(1)
IDT723611L15 IDT723611L20
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB – 66.7 – 50 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – MHz
tCLKH Pulse Duration, CLKA or CLKB HIGH 6 – 8 – ns
tCLKL Pulse Duration, CLKA or CLKB LOW 6 – 8 – ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4–5–ns
tENS1 CSA, W/RA, before CLKA↑; CSB, W/RB before CLKB↑ 6–6–ns
tENS2 ENA before CLKA↑; ENB before CLKB↑ 4–5–ns
tENS3 MBA before CLKA↑; ENB before CLKB↑ 4–5–ns
tPGS Setup Time, ODD/EVEN and PGB before CLKB↑
(1)
4–5–ns
tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑
(2)
5–6–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 1–1–ns
tENH1 CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑ 1–1–ns
tENH2 ENA after CLKA↑; ENB after CLKB↑ 1–1–ns
tENH3 MBA after CLKA↑; MBB after CLKB↑ 1–1–ns
tPGH Hold TIme, ODD/EVEN and PGB after CLKB↑
(2)
0–0–ns
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑
(3)
6–6–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns
tSKEW1
(4)
Skew Time, between CLKA↑ and CLKB↑ for EF, FF 8–8–ns
tSKEW2
(4)
Skew Time, between CLKA↑ and CLKB↑ for AE, AF 14 – 16 – ns
NOTES:
1. Industrial Temperature Range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a rising edge of CLKB that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
9
IDT723611
CMOS SyncFIFO
TM
64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
Commercial Com'l & Ind'l
(1)
IDT723611L15 IDT723611L20
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB – 66.7 – 50 MHz
tA Access Time, CLKB↑ to B0-B35 2 10 2 12 ns
tWFF Propagation Delay Time, CLKA↑ to FF 210212ns
tREF Propagation Delay Time, CLKB↑ to EF 210212ns
tPAE Propagation Delay Time, CLKB↑ to AE 210212ns
tPAF Propagation Delay Time, CLKA↑ to AF 210212ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ 19112ns
to MBF2 LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35
(2)
and CLKB↑ to A0-A35
(3)
312314ns
tMDV Propagation Delay Time, MBB to B0-B35 Valid 1 11 1 11.5 ns
t
PDPE Propagation Delay Time, A0-A35 Valid to PEFA Valid; B0-B35 Valid to 3 12 3 13 ns
PEFB Valid
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 311312ns
tPOPB
(4)
Propagation Delay Time, ODD/EVEN to Parity Bits (A8, A17, A26, A35) and 2 12 2 13 ns
(B8, B17, B26, B35)
tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB,112113ns
ENB, W/RB, MBB, or PGB to PEFB
tPEPB
(4)
Propagation Delay Time, CSA, ENA W/RA, MBA, or PGA to Parity Bits (A8, A17, 3 14 3 15 ns
A26, A35); CSB, ENB, W/RB, MBB, or PGB to ParityBits (B8, B17, B26, B35)
tRSF Propagation Delay Time, RST to AE LOW and (AF, MBF1, MBF2) HIGH 1 15 1 20 ns
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB210212ns
HIGH to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH 1 9 1 10 ns
or W/RB LOW to B0-B35 at high impedance
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3 Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when reading data from a mail register.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
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IDT723611L15PQF

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Description:
IC FIFO 64X36 SYNC 15NS 132QFP
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