RHYTHM R3910
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SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Value Units
Operating Temperature Range 0 to +40 °C
Storage Temperature Range −20 to +70 °C
Absolute Maximum Power Dissipation 50 mW
Maximum Operating Supply Voltage 1.65 VDC
Absolute Maximum Supply Voltage 1.8 VDC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
WARNING: Electrostatic Sensitive Device − Do not open packages or handle except at a static−free workstation.
WARNING: Moisture Sensitive Device − RoHS Compliant; Level 4 MSL. Do not open packages except under controlled conditions.
Table 2. ELECTRICAL CHARACTERISTICS (Supply Voltage V
B
= 1.25 V; Temperature = 25°C)
Parameter
Symbol Conditions Min Typ Max Units
Minimum Operating Supply Voltage V
BOFF
Ramp down, audio path 0.93 0.95 0.97
V
Ramp down, control logic 0.77 0.80 0.83
Supply Voltage Turn On Threshold V
BON
Ramp up, zinc−air 1.06 1.10 1.16
V
Ramp up, NiMH 1.16 1.20 1.24
Hybrid Current
All functions, 32 kHz sampling rate 665 mA
All functions, 16 kHz sampling rate 575
EEPROM Burn Cycles 100 k cycles
Low Frequency System Limit 125 Hz
High Frequency System Limit 16 kHz
Total Harmonic Distortion THD V
IN
= −40 dBV 1 %
THD at Maximum Input THD
M
V
IN
= −15 dBV, HRX − ON 3 %
Clock Frequency f
CLK
3.973 4.096 4.218 MHz
REGULATOR
Regulator Voltage
V
REG
0.87 0.90 0.93 V
System PSRR PSRR
SYS
1 kHz, Input referred, HRX enabled 70 dB
INPUT
Input Referred Noise
IRN Bandwidth 100 Hz − 8 kHz −108 −106 dBV
Input Impedance Z
IN
1 kHz 3
MW
Anti−aliasing Filter Rejection f = [DC − 112 kHz], V
IN
= −40 dBV 80 dB
Crosstalk Between both A/D and Mux 60 dB
Maximum Input Level −15 −13 dBV
Analogue Input Voltage Range
V
AN_IN
V
IN1
, V
IN2
, Al 0 800
mV
V
AN_TIN
T
IN
−100 800
Input Dynamic Range HRX − ON Bandwidth
100 Hz − 8 kHz
95 96 dB
Audio Sampling Rate 8 48 kHz
OUTPUT
D/A Dynamic Range
100 Hz − 8 kHz 88 dB
Output Impedance Z
OUT
10 13
W
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Table 2. ELECTRICAL CHARACTERISTICS (Supply Voltage V
B
= 1.25 V; Temperature = 25°C) (continued)
Parameter UnitsMaxTypMinConditionsSymbol
CONTROL A/D
Resolution (monotonic)
7 bits
Zero Scale Level 0 V
Full Scale Level V
REG
V
VOLUME CONTROL
Volume Control Resistance
R
VC
Three−terminal connection 200 1000
kW
Volume Control Range 42 dB
PC_SDA INPUT
Logic 0 Voltage
0 0.3 V
Logic 1 Voltage 1 1.25 V
PC_SDA OUTPUT
Stand−by Pull Up Current
Creftrim = 6 3 5 6.5
mA
Sync Pull Up Current Creftrim = 6 748 880 1020
mA
Max Sync Pull Up Current Creftrim = 15 1380
mA
Min Sync Pull Up Current Creftrim = 0 550
mA
Logic 0 Current (Pull Down) Creftrim = 6 374 440 506
mA
Logic 1 Current (Pull Up) Creftrim = 6 374 440 506
mA
Synchronization Time
(Synchronization Pulse Width)
T
SYNC
Baud = 0 237 250 263 ms
Baud = 1 118 125 132
Baud = 2 59 62.5 66
Baud = 3 29.76 31.25 32.81
Baud = 4 14.88 15.63 16.41
Baud = 5 7.44 7.81 8.20
Baud = 6 3.72 3.91 4.10
Baud = 7 1.86 1.95 2.05
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
Table 3. I
2
C TIMING
Parameter Symbol
Standard Mode Fast Mode
Units
Min Max Min Max
Clock Frequency f
PC_CLK
0 100 0 400 kHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
t
HD;STA
4.0 0.6
msec
LOW Period of the PC_CLK Clock t
LOW
4.7
msec
HIGH Period of the PC_CLK Clock t
HIGH
4.0
msec
Set−up time for a repeated START condition t
SU;STA
4.7
msec
Data Hold Time:
for CBUS Compatible Masters
for I
2
C−bus Devices
t
HD;DAT
5.0
0 (Note 1)
3.45 (Note 2)
0 (Note 1)
0.9 (Note 2)
msec
Data set−up time t
SU;DAT
250 100 nsec
Rise time of both PC_SDA and PC_CLK signals t
r
1000 20 + 0.1 C
b
(Note 4)
300 nsec
Fall time of both PC_SDA and PC_CLK signals t
f
300 20 + 0.1 C
b
(Note 4)
300 nsec
Set−up time for STOP condition t
SU;STO
4.0 0.6 nsec
Bus free time between a STOP and
START condition
t
BUF
4.7 1.3
msec
Output fall time from V
IHmin
to V
ILmax
with a bus
capacitance from 10 pF to 400 pF
t
of
250 20 + 0.1 C
b
250 nsec
Pulse width of spikes which must be suppressed
by the input filter
t
SP
n/a n/a 0 50 nsec
Capacitive load for each bus line C
b
400 400 pF
1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.
2. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the PC_CLK signal.
3. A Fast−mode I
2
C−bus device can be used in a Standard−mode I
2
C−bus system, but the requirement t
SU;DAT
P250ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the
LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according
to the Standard−mode I
2
C−bus specification) before the PC_CLK line is released.
4. C
b
= total capacitance of one bus line in pF.

R3910-CFAB-E1B

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Audio DSPs PRECONFIG DSP: RHYTH
Lifecycle:
New from this manufacturer.
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