Function description TDA7703
10/32 Rev 1
2.7 Audio D/A converters
A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding
by the DSP.
2.8 VCO
The VCO is fully integrated without any external tuning component. It covers all FM
frequency bands including EU, US, Japan, EastEU and AM-bands including LW and MW.
2.9 PLL
The high speed tuning PLL is able to settle within about 300 µs.
The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.
2.10 Crystal oscillator
The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a
3
rd
overtone 37.05 MHz crystal.
2.11 DSP
The DSP and its hardware accelerators perform all the digital signal processing. The main
program is fixed in ROM. Control parameters are copied in RAM and are accessible and
modifiable there, thus allowing parametric performance optimization.
It performs:
digital down-conversion of IF
bandwidth selection with variable controlled bandwidth
FM noiseblanking
FM/AM demodulation with softmute, high-cut, weak signal processing and quality
detection
FM stereo decoding with stereo blend
TDA7703 Function description
Rev 1 11/32
2.12 IO interface pins
The TDA7703 has the following IO pins:
All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA
from the internal 3.3 V supply line.
2.13 Serial interface
The device is controlled with a standard I
2
C bus interface.
Through the serial bus the processing parameters can be modifed and the signal quality
parameters can be read out.
The operation of the device is handled through high level commands sent by the main car-
radio µP through the serial interface, which allow to simplify the operations carried out in the
main µP. The high level commands include among others:
set frequency (which allows to avoid computing the PLL divider factors);
start seek (the seek operation can be carried out by the TDA7703 in a completely
autonomous fashion).
The serial bus communication configuration is set by forcing pin 29 (BUSSET) to ground
when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset mode).
The voltage level forced to pin 29 must be released to start the system operation a suitable
time after the RSTN line has gone high. The I
2
C address is 0xC2 (write) / 0xC3 (read).
The status of pin 29 during the reset phase can be set to low by not forcing any voltage on it
from outside, as a 50 kΩ internal pull-down resistors is present.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
additional time T
reset
(see Section 3.4.6).
I
2
C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see Communication Protocol Manual for frame structure description):
Figure 3. I
2
C "write" sequence
SDA pin 26 serial communication with µP
SCL pin 27 serial communication with µP
BUSSET pin 29 serial communication with µP
RSTN pin 30 reset pin driven by µP
ACK
data
STOP
clk1
clk2
clk8
clk9
clk1
clk2
START
ACK
d7
d6
address
a0
d0
clk8
clk9
a6
SCL
SDA
Function description TDA7703
12/32 Rev 1
The sequence consists of the following phases:
START: SDA line transitioning from H to L with SCL fixed H. This signifies a new
transmission is starting;
data latching: on the rising SCL edge. The SDA line can transition only when SCL is
low (otherwise its transitions are interpreted as either a START or a STOP transition);
ACKnowledge: on the 9
th
SCL pulse the µP keeps the SDA line H, and the TDA7703
pulls it down if communication has been successful. Lack of the acknowledge pulse
generation from the TDA7703 means that the communication has failed;
a chip address byte must be sent at the beginning of the transmission. The value is C2
for "write";
as many data bytes as needed can follow the address before the communication is
terminated. See the next section for details on the frame format;
STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the
transmission.
Red lines represent transmissions from the TDA7703 to the µP.
A "read" communication example is shown in the figure below, for an unspecified number of
data bytes (see later on for frame structure decription):
Figure 4. I
2
C "read" sequence
The sequence is very similar to the "write" one and has the same constraints for start, stop,
data latching. The differences follow:
a chip address must always be sent by the µP to the TDA7703; the address must be
C3;
a header is transmitted after the chip address (the same happens for "write") before
data are transferred from the TDA7703 to the µP. See the Communication Protocol
Manual for details on the frame format;
when data are transmitted from the TDA7703 to the µP, the µP keeps the SDA line H;
the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the
TDA7703 to the µP. Failure of the µP to generate an ACK pulse on the 9
th
CLK pulse
has the same effect on the TDA7703 as a STOP.
The max. clock speed is 500 kbit/s.
SDA
a7
a6
a0
d7
d6
d0
SCL
clk1
clk2
clk8
clk9
clk1
clk2
clk8
clk9
START
address
ACK
data
ACK
STOP

TDA7703TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Tuners AM FM Radio Tuner VCO PLL Dig IF
Lifecycle:
New from this manufacturer.
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