Electrical specifications TDA7703
16/32 Rev 1
3.4.4 Phase locked loop
3.4.5 Audio DAC
3.4.6 IO interface pins
Table 9. Phase locked loop
Symbol Parameter Test condition Min Typ Max Units
T
settle
Settling time FM Δf < 10 kHz 300 µs
FM step FM frequency step 5 kHz
AM step AM frequency step 500 Hz
Table 10. Audio DAC
Symbol Parameter Test condition Min Typ Max Units
V
out
Output voltage
AM 90% modulation;
FM 75 kHz deviation.
400 Hz audio frequency
300 mVrms
BW Bandwidth 1 dB attenuation 15 KHz
R
out
Output resistance 600 750 900 Ω
Table 11. IO interface pins
Symbol Parameter Test condition Min Typ Max Units
High level output voltage I
out
= 500µA 2.9 3.2 V
Low level output voltage I
out
= -1mA 0.1 0.3 V
Input voltage range 0 3.5 V
High level input voltage 2.0 V
Low level input voltage 0.8 V
T
reset
Reset time
Minimum time during which
pin RSTN must be low so as
to reset the device
10 µs
T
latch
Boot mode configuration latch
time
Minimum time during which
the voltage applied at pin 29
must be kept in order to latch
the correct boot mode (serial
bus configuration)
10 µs
TDA7703 Electrical specifications
Rev 1 17/32
3.4.7 I
2
C interface
The parameters of the following table are defined as in Figure 5.
Figure 5. I
2
C bus timing diagram
Table 12. I
2
C interface
Symbol Parameter Test condition Min Typ Max Units
f
SCL
SCL Clock frequency 500 kHz
t
AA
SCL low to SDA data valid 0.3 µs
t
buf
time the bus must be kept free
before a new transmisison
1.3 µs
t
HD-STA
START condition hold time 0.6 µs
t
LOW
Clock low period 1.3 µs
t
HIGH
Clock high period 0.6 µs
t
SU-SDA
START condition setup time 0.1 µs
t
HD-DAT
Data input hold time 0.3 0.9 µs
t
SU-DAT
Data input setup time 0.1 µs
t
R
SDA & SCL rise time 0.3 µs
t
F
SDA & SCL fall time 0.3 µs
t
SU-STOP
Stop condition setup time 0.6 µs
t
DH
Data out time 0.3 µs
D95AU378A
t
HIGH
t
R
t
LOW
t
F
SCL
SDA IN
SDA OUT
t
SU-STA
t
HD-SDA
t
HD-DAT
t
SU-DAT
t
SU-STOP
t
buf
t
AA
t
DH
Electrical specifications TDA7703
18/32 Rev 1
3.5 Overall system performance
All measurements obtained with application of Figure 9 unless otherwise specified.
3.5.1 FM overall system performance
Antenna level equivalence: 0 dBµV = 1 µV
rms
(Antenna terminal voltage with 50 Ω source).
Figure 6. FM input set-up
Input level referred to signal generator loaded with 50 Ω (V
rf
, node 'A'); no antenna dummy;
AM input not connected. F
rf
= 98.1 MHz, V
rf
= 60 dBµV, mono modulation, f
dev
= 40 kHz,
f
audio
= 1 kHz. De-emphasis = 50 µs. Unless otherwise specified
Table 13. FM overall system performance
Parameter Test condition Min Typ Max Units
Tuning range FM Eu
(can be modified by the user)
87.5 108 MHz
Tuning step FM Eu 100 kHz
Tuning range FM US 87.5 107.9 MHz
Tuning step FM US 200 kHz
Tuning range FM Jp 76 90 MHz
Tuning step FM Jp 100 kHz
Tuning range FM EEu 65 74 MHz
Tuning step FM EEu 100 kHz
Sensitivity S/N =26dB -3 0 dBµV
Ultimate S/N
@ 60 dBµV, mono 72 75 dB
@ 60 dBµV,
Deviation = 75 kHz, mono
77 80 dB
@ 60 dBµV, stereo 70 73 dB
Distortion Deviation= 75 kHz 0.15 %
Max deviation THD=3% 120 kHz
Adjacent channel selectivity
(V
u
/V
d
)
ΔF=100 kHz, SINAD=30 dB
desired 40 dBµV, dev=40kHz,
400Hz
undesired. dev=40kHz, 1KHz
13 dB
Alternate channel selectivity
(V
u
/V
d
)
ΔF=200 kHz, SINAD=30 dB
desired 40 dBµV,
dev=40 kHz, 400 Hz
undesired. dev=40kHz, 1kHz
62 dB
V
rf
+ 6dB
PCB
UNDER
TEST
50
Ω
V
rf
+ 6dB
V
rf
50
Ω
50
Ω
A

TDA7703TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Tuners AM FM Radio Tuner VCO PLL Dig IF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet