NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
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11
Plugging Equations 7 and 8 into Equation 6 leads to
t Vds(t) u+ Vin
and thus,
P
DSS
+ Vin ICC1
(eq. 9)
.
The worse case occurs at high line, when Vin equals
370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can
expect a DSS dissipation around 407 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds that number.
In that case, we recommend to add an auxiliary winding in
order to offer more dissipation room to the power MOSFET.
Please read application note AND8125/D, “Evaluating
the Power Capability of the NCP101X Members” to help in
selecting the right part/configuration for your application.
Lowering the Standby Power with an Auxiliary Winding
The DSS operation can bother the designer when its
dissipation is too high and extremely low standby power is
a must. In both cases, one can connect an auxiliary winding
to disable the self−supply. The current source then ensures
the startup sequence only and stays in the off state as long as
V
CC
does not drop below VCC
ON
or 7.5 V. Figure 20 shows
that the insertion of a resistor (Rlimit) between the auxiliary
DC level and the V
CC
pin is mandatory to not damage the
internal 8.7 V active Zener diode during an overshoot for
instance (absolute maximum current is 15 mA) and to
implement the fail−safe optocoupler protection as offered by
the active clamp. Please note that there cannot be bad
interaction between the clamping voltage of the internal
Zener and VCC
OFF
since this clamping voltage is actually
built on top of VCC
OFF
with a fixed amount of offset
(200 mV typical).
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop to below
10 V (Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency refueling rate of the V
CC
capacitor is not
enough to keep a constant auxiliary voltage. Figure 21
portrays a typical scope shot of a SMPS entering deep
standby (output unloaded). So care must be taken when
calculating Rlimit 1) to not trigger the V
CC
over current
latch [by injecting 6.3 mA (min. value) into the active
clamp] in normal operation but 2) not to drop too much
voltage over Rlimit when entering standby. Otherwise the
DSS could reactivate and the standby performance would
degrade. We are thus able to bound Rlimit between two
equations:
Vnom * Vclamp
Itrip
v Rlimit v
Vstby * VCC
ON
ICC1
(eq. 10)
Where:
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.
Itrip is the current corresponding to the nominal operation.
It must be selected to avoid false tripping in overshoot
conditions.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby almost does not switch.
VCC
ON
is the level above which Vaux must be maintained
to keep the DSS in the OFF mode. It is good to shoot around
8.0 V in order to offer an adequate design margin, e.g. to not
reactivate the startup source (which is not a problem in itself
if low standby power does not matter).
Since Rlimit shall not bother the controller in standby, e.g.
keep Vaux to around 8.0 V (as selected above), we purposely
select a Vnom well above this value. As explained before,
experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8.0 V when in standby
(Rlimit also drops voltage in standby…). Plugging the
values in Equation 10 gives the limits within which Rlimit
shall be selected:
*
6.3 m
v Rlimit v
*
1.1 m
(eq. 11
1.8 k t Rlimit t 3.6 k
, that is to say:
If we design a power supply delivering 12 V, then the ratio
between auxiliary and power must be: 12/20 = 0.6. The OVP
latch will activate when the clamp current exceeds 6.3 mA.
This will occur when Vaux increases to: 8.7 V + 1.8 k x
(6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V +
3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the
power output, it will respectively give 22.2 x 0.6 = 13.3 V
and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit
value will allow the selection of a given overvoltage output
level. Theoretically predicting the auxiliary drop from
nominal to standby is an almost impossible exercise since
many parameters are involved, including the converter time
constants. Fine tuning of Rlimit thus requires a few
iterations and experiments on a breadboard to check Vaux
variations but also output voltage excursion in fault. Once
properly adjusted, the fail−safe protection will preclude any
lethal voltage runaways in case a problem would occur in the
feedback loop.
When an OVP occurs, all switching pulses are
permanently disabled, the output voltage thus drops to zero.
The V
CC
cycles up and down between 8.5–4.7 V and stays
in this state until the user unplugs the power supply and
forces V
CC
to drop below 3.0 V (VCC
reset
). Below this
value, the internal OVP latch is reset and when the high
voltage is reapplied, a new startup sequence can take place
in an attempt to restart the converter.
