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NCP1014APL065R2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
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13
Figure 22. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation
100%
Peak current
at nominal power
25%
Skip−cycle
current limit
Full power operation involves the nominal switching
frequency and thus avoids any noise when running.
Experiments carried on a 5.0 W universal mains board
unveiled a standby power of 300 mW @ 230 Vac with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.
Frequency Jittering for Improved EMI Signature
By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers
the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
EMI sweep is implemented by routing the V
CC
ripple
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is "3.3% of the nominal
frequency. With a 1.0 V peak−to−peak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
increase as V
CC
rises or decrease as V
CC
ramps down.
Figure 23 portrays the behavior we have adopted.
Figure 23. The V
CC
ripple is used to introduce a frequency jittering on the internal oscillator sawtooth.
Here, a 65 kHz version was selected.
V
CC
Ripple
VCC
OFF
67.15 kHz
65 kHz
62.85 kHz
VCC
ON
Internal Sawtooth
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
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14
Soft−Start
The NCP101X features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
V
CC
reaches VCC
OFF
, the peak current is gradually
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1.0 ms
and further to that time period, the peak current limit is
blocked to the maximum until the supply enters regulation.
The soft−start is also activated during the over current burst
(OCP) sequence. Every restart attempt is followed by a
soft−start activation. Generally speaking, the soft−start will
be activated when V
CC
ramps up either from zero (fresh
power−on sequence) or 4.7 V, the latch−off voltage
occurring during OCP. Figure 24 portrays the soft−start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
Figure 24. Soft−Start is activated during a startup sequence or an OCP condition.
0 V (Fresh PON)
or
4.7 V (Overload)
V
CC
8.5 V
Current
Sense
Max Ip
1.0 ms
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the internal skip level
(Vskip), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 25 depicts the
application example.
Figure 25. A non−latching shutdown where pulses are stopped as long as the NPN is biased.
ON/OFF
27
3
45
18
Drain
+
CV
cc
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
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15
Full Latching Shutdown
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (overtemperature
or overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the OVP level exceeds the Zener breakdown
voltage, the NPN biases the PNP and fires the equivalent
SCR, permanently bringing down the FB pin. The
switching pulses are disabled until the user unplugs the
power supply.
Figure 26. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
27
3
45
18
Drain
+
CV
cc
BAT54
10 k
10 k
OVP
Rhold
12 k
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to let
the V
CC
ramp up (8.5 V) and down (7.5 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Power Dissipation and Heatsinking
The NCP101X welcomes two dissipating terms, the DSS
current−source (when active) and the MOSFET. Thus,
Ptot = P
DSS
+ P
MOSFET
. When the PDIP−7 package is
surrounded by copper, it becomes possible to drop its
thermal resistance junction−to−ambient, R
q
JA
down
to 75°C/W and thus dissipate more power. The
maximum power the device can thus evacuate is:
Pmax +
T
Jmax
* Tambmax
R
qJA
(eq. 12)
which gives around
1.0 W for an ambient of 50°C. The losses inherent to the
MOSFET R
DSon
can be evaluated using the following
formula:
Pmos +
1
3
·Ip
2
·d·R
DSon
(eq. 13)
, where Ip
is the worse case peak current (at the lowest line input), d is
the converter operating duty−cycle and R
DSon
, the
MOSFET resistance for T
J
= 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turn−on losses are null (the primary
current is zero when you restart the MOSFET). Figure 27
gives a possible layout to help drop the thermal resistance.
When measured on a 35 mm (1 oz) copper thickness PCB,
we obtained a thermal resistance of 75°C/W.
Figure 27. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

NCP1014APL065R2G

Mfr. #:
Buy NCP1014APL065R2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers ANA 1 FREQ GULL WING
Lifecycle:
New from this manufacturer.
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