MAX5230/MAX5231
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5230 (continued)
(V
DD
= +2.7V to +3.6V, OS_ = AGND = DGND = 0, R
L
= 5k, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Reference External Load Regulation V
OUT
/I
OUT
0 I
OUT
100µA (sourcing) 0.1 2 µV/µA
Reference Short-Circuit Current 4 mA
DIGITAL INPUTS
Input High Voltage V
IH
0.7 x V
DD
V
Input Low Voltage V
IL
0.3 x V
DD
V
Input Hysteresis V
HYS
200 mV
Input Leakage Current I
IN
Digital inputs = 0 or V
DD
±A
Input Capacitance C
IN
8pF
DIGITAL OUTPUTS
Output High Voltage V
OH
I
SOURCE
= 2mA 2.3 V
Output Low Voltage V
OL
I
SINK
= 2mA 0.25 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR 0.6 V/µs
Voltage-Output Settling Time
To ±0.5 LSB, V
STEP
= ±2V
(V
DD
- 0.25V) V
OUT
0.25V
10 µs
Output-Voltage Swing (Note 5) 0 to V
DD
V
OS_ Input Resistance R
OS
83 121 k
Time Required for Output to Settle After
Turning on V
DD
(Note 6)
95 400 µs
Time Required for Output to Settle After
Exiting Full Power-Down (Note 6)
95 400 µs
Time Required for Output to Settle After
Exiting DAC Power-Down (Note 6)
12 160 µs
Digital Feedthrough
CS =V
DD
, f
SCLK
= 100kHz,
V
SCLK
= 3V
P-P
5 nV-s
Major-Carry Glitch Energy 90 nV-s
MAX5230/MAX5231
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
_______________________________________________________________________________________ 5
Note 1: Accuracy is guaranteed as shown in the following table:
Note 2: Offset is measured at the code closest to 10mV.
Note 3: Temperature coefficient is determined by the box method in which the maximum V
OUT
over the temperature range is
divided by T.
Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change
DAC B to full scale, and measure V
OUT
for DAC A. Repeat the same measurement with DAC A and DAC B interchanged.
DC crosstalk is the maximum V
OUT
measured.
Note 5: Accuracy is better than 1LSB for V
OUT_
= 10mV to V
DD
- 180mV.
Note 6: Guaranteed by design, not production tested.
Note 7: R
LOAD
= and digital inputs are at either V
DD
or DGND.
ACCURACY GUARANTEED
V
DD
(V)
FROM CODE TO CODE
3 20 4095
5 10 4095
TIMING CHARACTERISTICS—MAX5231
(V
DD
= +4.5V to +5.5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
(Figures 1 and 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
74 ns
SCLK Pulse Width High t
CH
30 ns
SCLK Pulse Width Low t
CL
30 ns
CS Fall to SCLK Rise Setup Time t
CSS
30 ns
SCLK Rise to CS Rise Hold Time t
CSH
0ns
DIN Setup Time t
DS
30 ns
DIN Hold Time t
DH
0ns
C
LOAD
= 200pF 45 100
SCLK Rise to DOUT Valid
Propagation Delay Time
t
DO1
C
LOAD
= 100pF 30
ns
C
LOAD
= 200pF 45 100
SCLK Fall to DOUT Valid
Propagation Delay Time
t
DO2
C
LOAD
= 100pF 30
ns
SCLK Rise to CS Fall Delay t
CS0
10 ns
CS Rise to SCLK Rise Hold Time t
CS1
30 ns
CS Pulse Width High t
CSW
75 ns
LDAC Pulse Width Low t
LDL
30 ns
CS Rise to LDAC Rise Hold Time t
CSLD
(Note 8) 40 ns
ELECTRICAL CHARACTERISTICS—MAX5230 (continued)
(V
DD
= +2.7V to +3.6V, OS_ = AGND = DGND = 0, R
L
= 5k, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Power-Supply Voltage V
DD
2.7 3.6 V
Power-Supply Current (Note 7) I
DD
420 475 µA
Full power-down mode 0.9 5
One DAC shutdown mode 320 360
Power-Supply Current in Power-Down
and Shutdown Modes (Note 7)
Both DACs shutdown mode 220 245
µA
MAX5230/MAX5231
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—MAX5230
(V
DD
= +2.7V to +3.6V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
(Figures 1 and 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
74 ns
SCLK Pulse Width High t
CH
30 ns
SCLK Pulse Width Low t
CL
30 ns
CS Fall to SCLK Rise Setup Time t
CSS
30 ns
SCLK Rise to CS Rise Hold Time t
CSH
0ns
DIN Setup Time t
DS
30 ns
DIN Hold Time t
DH
0ns
C
LOAD
= 200pF 60 200
SCLK Rise to DOUT Valid
Propagation Delay Time
t
DO1
C
LOAD
= 100pF 45
ns
C
LOAD
= 200pF 60 200
SCLK Fall to DOUT Valid
Propagation Delay Time
t
DO2
C
LOAD
= 100pF 45
ns
SCLK Rise to CS Fall Delay t
CS0
10 ns
CS Rise to SCLK Rise Hold Time t
CS1
30 ns
CS Pulse Width High t
CSW
75 ns
LDAC Pulse Width Low t
LDL
30 ns
CS Rise to LDAC Rise Hold Time t
CSLD
(Note 8) 75 ns
Note 8: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register
contents.
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5230)
MAX5230/MAX5231 toc01
DIGITAL INPUT CODE
INL (LSB)
40003500300025002000150010005000
-0.10
-0.05
0
0.05
0.10
0.15
-0.15
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5231)
MAX5230/MAX5231 toc02
DIGITAL INPUT CODE
INL (LSB)
40003500300025002000150010005000
-0.10
-0.05
0
0.05
0.10
0.15
-0.15
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5230)
MAX5230/MAX5231 toc03
DIGITAL INPUT CODE
DNL (LSB)
40003500300025002000150010005000
-0.283
-0.037
0.086
0.208
-0.160
Typical Operating Characteristics
(V
DD
= +3V (MAX5230), V
DD
= +5V (MAX5231), R
L
= 5k, C
L
= 100pF, OS_ = AGND, both DACs enabled with full-scale output code,
T
A
= +25°C, unless otherwise noted.)

MAX5230AEEE+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
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