2. Electrical Characteristics
2.1 Absolute Maximum Ratings*
Operating Temperature -40°C to +85°C
Storage Temperature -65°C to +150°C
Maximum Operating Voltage 6.0V
DC Output Current 5.0 mA
Voltage on any pin -0.5V to (VCC + 0.5V) -0.5V to (VCC + 0.5V)
Note:  Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of this specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.2 Reliability
The ATECC608A is fabricated with the Microchip high reliability of the CMOS EEPROM manufacturing
technology.
Table 2-1. EEPROM Reliability
Parameter
Min Typical Max Units
Write Endurance at +85°C (Each Byte) 400,000 Write Cycles
Data Retention at +55°C 10 Years
Data Retention at +35°C 30 50 Years
Read Endurance Unlimited Read Cycles
2.3 AC Parameters: All I/O Interfaces
Figure 2-1. AC Timing Diagram: All Interfaces
Data Comm
Wake
t
LIGNORE
t
HIGNORE
Noise
Suppresion
t
WLO
t
WHI
ATECC608A
Electrical Characteristics
© 2017 Microchip Technology Inc.
Datasheet Summary
DS40001977A-page 7
Table 2-2. AC Parameters: All I/O Interfaces
Parameter Symbol Direction Min Typ Max Unit Conditions
Power-Up
Delay
(2)
t
PU
To Crypto
Authentication
100 µs Minimum time between V
CC
> V
CC
min
prior to measurement of t
WLO
.
Wake Low
Duration
t
WLO
To Crypto
Authentication
60 µs
Wake High Delay
to Data Comm.
t
WHI
To Crypto
Authentication
1500 µs SDA should be stable high for this entire
duration.
High Side Glitch
Filter at Active
t
HIGNOR
E_A
To Crypto
Authentication
45
(1)
ns Pulses shorter than this in width will be
ignored by the device, regardless of its
state when active.
Low Side Glitch
Filter at Active
t
LIGNORE
_A
To Crypto
Authentication
45
(1)
ns Pulses shorter than this in width will be
ignored by the device, regardless of its
state when active.
Low Side Glitch
Filter at Sleep
t
LIGNORE
_S
To Crypto
Authentication
15
(1)
µs Pulses shorter than this in width will be
ignored by the device when in sleep mode.
Watchdog
Timeout
t
WATCHD
OG
To Crypto
Authentication
0.7 1.3 1.7 s Time from wake until device is forced into
sleep mode if Config.ChipMode.Bit2 is 0.
7.6 13 17 s Watchdog time : Config.ChipMode.Bit2 is 0.
Note: 
1. These parameters are guaranteed through characterization, but not tested.
2. The power-up delay will be significantly longer if Power-On self test is enabled in the configuration
zone.
2.3.1 AC Parameters: Single-Wire Interface
Figure 2-2. AC Timing Diagram: Single-Wire Interface
t
START
t
ZHI
t
ZLO
Logic Ø
t
START
t
BIT
Logic 1
t
START
t
TURNAROUND
t
START
SDA
Table 2-3. AC Parameters: Single-Wire Interface
Unless otherwise specified, applicable from T
A
= -40°C to +85°C, V
CC
= +2.0V to +5.5V, C
L
= 100 pF.
ATECC608A
Electrical Characteristics
© 2017 Microchip Technology Inc.
Datasheet Summary
DS40001977A-page 8
Parameter Symbol Direction Min. Typ. Max. Unit Conditions
Start Pulse
Duration
t
START
To Crypto
Authentication
4.10 4.34 4.56 µs
From Crypto
Authentication
4.60 6 8.60 µs
Zero
Transmission
High Pulse
t
ZHI
To Crypto
Authentication
4.10 4.34 4.56 µs
From Crypto
Authentication
4.60 6 8.60 µs
Zero
Transmission
Low Pulse
t
ZLO
To Crypto
Authentication
4.10 4.34 4.56 µs
From Crypto
Authentication
4.60 6 8.60 µs
Bit Time(1) t
BIT
To Crypto
Authentication
37 39 µs If the bit time exceeds t
TIMEOUT
then
ATECC608A may enter the sleep mode. .
From Crypto
Authentication
41 54 78 µs
Turn Around
Delay
t
TURNARO
UND
From Crypto
Authentication
64 96 131 µs ATECC608A will initiate the first low going
transition after this time interval following
the initial falling edge of the start pulse of
the last bit of the transmit flag.
To Crypto
Authentication
93 µs After ATECC608A transmits the last bit of a
group, system must wait this interval before
sending the first bit of a flag. It is measured
from the falling edge of the start pulse of the
last bit transmitted by ATECC608A .
IO Timeout t
TIMEOUT
To Crypto
Authentication
45 65 85 ms ATECC608A may transition to the sleep
mode if the bus is inactive longer than this
duration.
Note:  START, ZLO, ZHI, and BIT are designed to be compatible with a standard UART running at
230.4 Kbaud for both transmit and receive. The UART should be set to seven data bits, no parity and one
Stop bit.
ATECC608A
Electrical Characteristics
© 2017 Microchip Technology Inc.
Datasheet Summary
DS40001977A-page 9

ATECC608A-MAHCZ-T

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