standard Serial EEPROM; however, these can be easily copied with no way for the host to know if the
serial number is authentic or if it is a clone.
The ATECC608A features a wide array of defense mechanisms specifically designed to prevent physical
attacks on the device itself, or logical attacks on the data transmitted between the device and the system.
Hardware restrictions on the ways in which keys are used or generated provide further defense against
certain styles of attack.
1.3 Cryptographic Operation
The ATECC608A implements a complete asymmetric (public/private) key cryptographic signature solution
based upon Elliptic Curve Cryptography and the ECDSA signature protocol. The device features
hardware acceleration for the NIST standard P256 prime curve and supports the complete key life cycle
from high quality private key generation, to ECDSA signature generation, ECDH key agreement, and
ECDSA public key signature verification.
The hardware accelerator can implement such asymmetric cryptographic operations from ten to one-
thousand times faster than software running on standard microprocessors, without the usual high risk of
key exposure that is endemic to standard microprocessors.
The ATECC608A also implements AES-128, SHA256 and multiple SHA derivatives such as HMAC(SHA),
PRF (the key derivation function in TLS) and HKDF in hardware. Support is included for the Galois Field
Multiply (aka Ghash) to facilitate GCM encryption/decryption/authentication.
The device is designed to securely store multiple private keys along with their associated public keys and
certificates. The signature verification command can use any stored or an external ECC public key. Public
keys stored within the device can be configured to require validation via a certificate chain to speed-up
subsequent device authentications.
Random private key generation is supported internally within the device to ensure that the private key can
never be known outside of the device. The public key corresponding to a stored private key is always
returned when the key is generated and it may optionally be computed at a later time.
The ATECC608A can generate high-quality random numbers using its internal random number generator.
This sophisticated function includes runtime health testing designed to ensure that the values generated
from the internal noise source contain sufficient entropy at the current time, with the current device and
under the current voltage and temperature conditions. The random number generator is designed to meet
the requirements documented in the NIST 800-90A, 800-90B and 800-90C documents.
These random numbers can be employed for any purpose, including usage as part of the device’s crypto
protocols. Because each random number is guaranteed to be essentially unique from all numbers ever
generated on this or any other device, their inclusion in the protocol calculation ensures that replay
attacks (i.e. re-transmitting a previously successful transaction) will always fail.
The ATECC608A also supports a standard hash-based challenge-response protocol in order to allow its
use across a wide variety of additional applications. In its most basic instantiation, the system sends a
challenge to the device, which combines that challenge with a secret key via the MAC command and then
sends the response back to the system. The device uses a SHA-256 cryptographic hash algorithm to
make that combination so that an observer on the bus cannot derive the value of the secret key, but
preserving that ability of a recipient to verify that the response is correct by performing the same
calculation with a stored copy of the secret on the recipient’s system. There are a wide variety of
variations possible on this symmetric challenge/response theme.
ATECC608A
Introduction
© 2017 Microchip Technology Inc.
Datasheet Summary
DS40001977A-page 6
