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LTC3878IGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC3878
10
3878fa
applicaTions inForMaTion
The basic LTC3878 application circuit is shown on the first
page of this data sheet. External component selection is
largely determined by maximum load current and begins
with the selection of sense resistance and power MOSFET
switches. The LTC3878 uses the on-resistance of the syn
-
ch
ronous power MOSFET to determine the inductor current.
The desired ripple current and operating frequency largely
determines the inductor value. Finally, C
IN
is selected for its
ability to handle the large RMS current into the converter,
and C
OUT
is chosen with low enough ESR to meet output
voltage ripple and transient specifications.
Maximum V
DS
Sense Voltage and V
RNG
Pin
Inductor current is measured by sensing the bottom
MOSFET V
DS
voltage that appears between the PGND
and SW pins. The maximum allowed V
DS
sense voltage is
set by the voltage applied to the V
RNG
pin and is approxi-
mately equal to (0.133)V
RNG
. The current mode control
loop does not allow the inductor current valleys to exceed
(0.133)V
RNG
. In practice, one should allow margin, to ac-
count for variations in the LTC3878 and external component
values. A good guide for setting V
RNG
is:
V
RNG
= 7.5 • (Maximum V
DS
Sense Voltage)
An external resistive divider from INTV
CC
can be used
to set the voltage on the V
RNG
pin between 0.2V and 2V,
resulting in peak sense voltages between 26.6mV and
266mV. The wide peak voltage sense range allows for a
variety of applications and MOSFET choices. The V
RNG
pin
can also be tied to either SGND or INTV
CC
to force internal
defaults. When V
RNG
is tied to SGND, the device operates
at a valley current sense threshold of 93mV typical. If V
RNG
is tied to INTV
CC
, the device operates at a valley current
sense threshold of 186mV typical.
Power MOSFET Selection
The LTC3878 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
BR(DSS)
,
threshold voltage V
GS(TH)
, on-resistance R
DS(ON)
, re-
verse transfer capacitance C
RSS
and maximum current
I
DS(MAX)
.
The gate drive voltages are set by the 5.3V INTV
CC
supply.
Consequently, logic-level threshold MOSFETs must be used
in LTC3878 applications. If the input voltage is expected
to drop below 5V, then sub-logic level threshold MOSFETs
should be considered.
Using the bottom MOSFET as the current sense element
requires particular attention be paid to its on-resistance.
MOSFET on-resistance is typically specified with a maxi
-
mum value
R
DS(ON)(MAX)
at 25°C. In this case additional
margin is required to accommodate the rise in MOSFET
on-resistance with temperature.
R
Max V Sense Voltage
I
DS ON MAX
DS
OUT T
( )( )
•
=
ρ
The ρ
T
term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C, as shown in
Figure 1. For a maximum junction temperature of 100°C
using a value of
ρ
T
= 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
depends upon their respective duty cycles and the load
current. When the LTC3878 is operating in continuous
mode, the duty cycles for the MOSFETs are:
D
V
V
D
V V
V
TOP
OUT
IN
BOT
IN OUT
IN
=
=
–
Figure 1. R
DS(ON)
vs Temperature
JUNCTION TEMPERATURE (°C)
–50
R
T
NORMALIZED ON-RESISTANCE (Ω)
1.0
1.5
150
3878 F01
0.5
0
0
50
100
2.0
LTC3878
11
3878fa
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P D I R
V
TOP TOP OUT MAX TOP DS ON MAX
=
+
• • •
( ) ( ) ( )( )
2
ρ
τ
IIN
OUT MAX
MILLER
TGHIGH
INTVC
I
C
DR
V
2
2
( )
( )
CC MILLER
TGLOW
MILLER
OSC
BOT BO
V
DR
V
f
P D
–
+
=
TT OUT MAX BOT DS ON MAX
I R• • •
( ) ( ) ( )( )
2
ρ
τ
DR
TGHIGH
is pull-up driver resistance and DR
TGLOW
is the
TG driver pull-down resistance. V
MILLER
is the Miller ef-
fect V
GS
voltage and is taken graphically from the power
MOSFET data sheet.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate charge”
curve included on the most data sheets (Figure 2). The
curve is generated by forcing a constant input current
into the gate of a common source, current source, loaded
stage and then plotting the gate versus time. The initial
slope is the effect of the gate-to-source and gate-to-drain
capacitance. The flat portion of the curve is the result of the
Miller multiplication effect of the drain-to-gate capacitance
as the drain drops the voltage across the current source
load. The upper sloping line is due to the drain-to-gate
accumulation capacitance and the gate-to-source capaci
-
tance. The
Miller charge (the increase in coulombs on the
horizontal axis from a to b while the curve is flat) is speci
-
fied from
a given V
DS
drain voltage, but can be adjusted
for different V
DS
voltages by multiplying by the ratio of
the application V
DS
to the curve specified V
DS
values. A
way to estimate the C
MILLER
term is to take the change in
gate charge from points a and b or the parameter Q
GD
on
a manufacturers data sheet and divide by the specified
V
DS
test voltage, V
DS(TEST)
.
C
Q
V
MILLER
GD
DS TEST
=
( )
C
MILLER
is the most important selection criteria for deter-
mining the transition loss term in the top MOSFET but is
not directly specified on MOSFET data sheets.
Both MOSFETs have I
2
R power loss, and the top MOSFET
includes an additional term for transition loss, which are
highest at high input voltages. For V
IN
< 20V, the high cur-
rent efficiency generally improves with larger MOSFETs,
while for V
IN
> 20V, the transition losses rapidly increase
to the point that the use of a higher R
DS(ON)
device with
lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Lowering the operating fre
-
qu
ency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The operating frequency of LTC3878 applications is de
-
termined implicitly by the one-shot timer that controls the
on-time, t
ON
, of the top MOSFET switch. The on-time is
set by the current into the I
ON
pin according to:
t
V
I
pF
ON
ION
=
( )
0 7
10
.
Tying a resistor R
ON
from V
IN
to the I
ON
pin yields an
on-time inversely proportional to V
IN
. For a step-down
converter, this results in pseudo fixed frequency operation
as the input supply varies.
f
V
V R pF
Hz
OP
OUT
ON
=
( )
0 7 10. •
[ ]
applicaTions inForMaTion
Figure 2. Gate Charge Characteristic
+
–
V
DS
V
IN
3878 F02
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
LTC3878
12
3878fa
applicaTions inForMaTion
Figure 3 shows how R
ON
relates to switching frequency
for several common output voltages.
When designing for pseudo fixed frequency, there is sys-
tematic error because the I
ON
pin voltage is approximately
0.7V, not zero. This causes the I
ON
current to be inversely
proportional to (V
IN
– 0.7V) and not V
IN
. The I
ON
current
error increases as V
IN
decreases. To correct this error, an
additional resistor R
ON2
can be connected from the I
ON
pin to the 5.3V INTV
CC
supply.
R
V V
V
R
ON ON2
5 3 0 7
0 7
=
. – .
.
Likewise, the maximum frequency of operation is deter-
mined by the fixed on-time, t
ON
, and the minimum off-time,
t
OFF(MIN)
. The fixed on-time is determined by dividing the
duty factor by the nominal frequency of operation:
f
V
V f
t
Hz
MAX
OUT
IN OP
OFF MIN
=
+
1
•
[ ]
( )
The LTC3878 is a PFM (pulse frequency mode) regula-
tor where pulse density is modulated, not pulse width.
Consequently, frequency increases with a load step and
decreases with a load release. The steady-state operating
frequency, f
OP
, should be set sufficiently below f
MAX
to
allow for device tolerances and transient response.
Inductor Value Calculation
Given the desired input and output voltages, the induc
-
tor value and operation frequency determine the ripple
current:
∆I
V
f L
V
V
L
OUT
OP
OUT
IN
=
•
–1
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
Figure 4. Maximum Switching Frequency vs Duty Cycle
Figure 3. Switching Frequency vs R
ON
Minimum Off-Time and Dropout Operation
The minimum off-time, t
OFF(MIN)
, is the shortest time
required for the LTC3878 to turn on the bottom MOSFET,
trip the current comparator and then turn off the bottom
MOSFET. This time is typically about 220ns. The minimum
off-time limit imposes a maximum duty cycle of t
ON
/
(t
ON
+ t
OFF(MIN)
). If the maximum duty cycle is reached,
due to a drooping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
V V
t t
t
IN MIN OUT
ON OFF MIN
ON
( )
( )
=
+
A plot of maximum duty cycle vs. frequency is shown in
Figure 4.
DUTY CYCLE (V
OUT
/V
IN
)
DROPOUT
REGION
SWITCHING FREQUENCY (MHz)
2
3
3878 F04
1
0
0 0.25 0.50 0.75 1
4
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LTC3878IGN#PBF

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Description:
Switching Voltage Regulators Wide Operating Range No Rsense Step-Down Controller
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