KSZ8863MLL/FLL/RLL Evaluation Board User’s Guide
Micrel, Inc. January 11, 2011
Confidential Rev. 1.1
9/10
See the Micrel Switch Configuration Software User Guide for details.
4.4 10/100 Ethernet PHY Ports (KSZ8863MLL/RLL)
There are two 10/100 Ethernet PHY ports on the KSZ8863MLL/RLL evaluation board. The ports
can be connected to an Ethernet traffic generator or analyzer via standard RJ-45 connectors
using CAT-5 cables. Each port can be used as either an uplink or downlink. Both ports support
auto MDI/MDI-X, eliminating the need for cross over cables.
4.5 100FX Fiber Port (KSZ8863FLL)
There are two 100FX PHY ports on the KSZ8863FLL evaluation board. The ports can be
connected to an Ethernet traffic generator or analyzer via fiber transceiver and fiber cable. The
fiber signal threshold can be set by register 192 bit 6(Port1) and bit 7(Port2). If the bits are 1, the
threshold will be set to 2.0V, Otherwise it is 1.25V.The resister R76 also need to be adjusted if
the FXSD signal value from the fiber module doesn’t meet the fiber signal threshold spec.
4.6 LED Indicators
There is one column of LED indicator for one column for port 2. The LED indicators are
programmable to three different modes. LED mode is selected through register 195 bit [5:4]
setting. The LED mode definitions are specified in Table 5. See Figure 1 for the LEDs’ orientation
on the KSZ8863MLL/FLL/RLL evaluation board.
Table 5: LED Modes
Register 195 Bit[5:4]
00 01 10 11
PxLED1 = Speed PxLED1 = Active PxLED1 = Duplex PxLED1 = Duplex
PxLED0 = Link/Active PxLED0 = Link PxLED0 = Link/Active PxLED0 = Link
The KSZ8863MLL/FLL/RLL evaluation board provides two LEDs (PxLED1, PxLED0) for each
PHY port.
The KSZ8863MLL/FLL/RLL evaluation board also has a power LED (D3) for the 3.3V power
supply. When D3 is lit, the board’s 3.3V power supply is “on”.
4.7 MII Port Configuration (KSZ8863MLL/FLL)
The evaluation board provides access to the KSZ8863MLL/FLL/RLL’s third MAC via the MII port
interfaces. The MAC can be configured to MII PHY mode and MII MAC mode via register 53 bit 7.
The default of the bit is 0 for MII PHY mode.
In MII PHY mode, the MII transmit and receive signals will be on J3, the male MII port connectors.
This mode is usually used to connect the KSZ8863MLL/FLL/RLL to an external MAC processor.
In MII MAC mode, the MII transmit and receive signals will be on J4, the female MII port
connector. This interface is normally used to connect the KSZ8863MLL/FLL/RLL to an external
PHY, for example the Micrel KSZ8041NL.
4.8 RMII Port Configuration (KSZ8863RLL)
In RMII interface, the 50MHz reference clock can be provide by the KSZ8863RLL or by the link
partner. When pin 1-2 of JP28 is closed, the reference clock will be output from REFCLKO on
