CS7054
http://onsemi.com
6
APPLICATIONS INFORMATION
THEORY OF OPERATION
Oscillator
The IC sets up a constant frequency triangle wave at the
C
OSC
lead whose frequency is determined by the external
components R
OSC
and C
OSC
by the following equation:
Frequency
0.83
R
OSC
C
OSC
The peak and valley of the triangle wave are proportional
to V
CC
by the following:
V
VALLEY
0.2 V
CC
V
PEAK
0.8 V
CC
This is required to make the voltage compensation
function properly. In order to keep the frequency of the
oscillator constant the current that charges C
OSC
must also
vary with supply. R
OSC
sets up the current which charges
C
OSC
. The voltage across R
OSC
is 50% of V
CC
and
therefore:
I
ROSC
0.5
V
CC
R
OSC
I
ROSC
is multiplied by two (2) internally and transferred
to the C
OSC
lead. Therefore:
I
COSC
V
CC
R
OSC
The period of the oscillator is:
T 2C
OSC
V
PEAK
V
VALLEY
I
COSC
The R
OSC
and C
OSC
components can be varied to create
frequencies over the range of 15 Hz to 25 kHz. With the
suggested values of 105 kΩ and 390 pF for R
OSC
and C
OSC
respectively, the nominal frequency will be approximately
20 kHz. I
ROSC
, at V
CC
= 14 V, will be 66.7 µA. I
ROSC
should
not change over a more than 2:1 ratio and therefore C
OSC
should be changed to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates ON Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations in
the supply voltage. The duty cycle is varied based upon the
input voltage and supply voltage by the following equation:
Duty Cycle 100%
2.8 V
CTL
V
CC
An internal DC voltage equal to:
V
DC
(1.683 V
CTL
) V
VALLEY
is compared to the oscillator voltage to produce the
compensated duty cycle. The transfer is set up so that at V
CC
= 14 V the duty will equal V
CTL
divided by V
REG
. For
example at V
CC
= 14 V, V
REG
= 5.0 V and V
CTL
= 2.5 V, the
duty cycle would be 50% at the output. This would place a
7.0 V average voltage across the load. If V
CC
then drops to
10 V, the IC would change the duty cycle to 70% and hence
keep the average load voltage at 7.0 V.
Figure 8. Voltage Compensation
0
20 50 100
CTL Voltage (% of V
REG
)
120
100
80
60
40
Duty Cycle (%)
10 30 40 60 70 80 90
20
V
CC
= 8.0 V
V
CC
= 14 V
V
CC
= 16 V
5.0 V Linear Regulator
There is a 5.0 V, 5.0 mA linear regulator available at the
V
REG
lead for external use. This voltage acts as a reference
for many internal and external functions. It has a drop out of
approximately 1.5 V at room temperature and does not
require an external capacitor for stability.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the I
SENSE+
and I
SENSE–
leads. The
differential voltage across these two leads is amplified
internally and compared to the voltage at the I
ADJ
lead. The
gain, A
V
, is set internally and externally by the following
equation:
A
V
V
I(ADJ)
I
SENSE
I
SENSE
37000
1000 R
CS
The current limit (I
LIM
) is set by the external current sense
resistor (R
SENSE
) placed across the I
SENSE+
and I
SENSE–
terminals and the voltage at the I
ADJ
lead.
I
LIM
1000 R
CS
37000
V
I(ADJ)
R
SENSE
The R
CS
resistors and C
CS
components form a differential
low pass filter which filters out high frequency noise
generated by the switching of the external MOSFET and the
associated lead noise. R
CS
also forms an error term in the
gain of the I
LIM
equation because the I
SENSE+
and I
SENSE–
