CS7054
http://onsemi.com
7
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50 µA while the
chip is in run mode. R
CS
should be much less than 1000 Ω
to minimize error in the I
LIM
equation. I
ADJ
should be biased
between 1.0 V and 4.0 V.
When the current through the external MOSFET exceeds
I
LIM
, an internal latch is set and the output pulls the gate of
the MOSFET low for the remainder of the oscillator cycle
(fault mode). At the start of the next cycle, the latch is reset
and the IC reverts back to run mode until another fault
occurs. If a number of faults occur in a given period of time,
the IC “times out” and disables the MOSFET for a long
period of time to let it cool off. This is accomplished by
charging the C
FLT
capacitor each time an over current
condition occurs. If a cycle goes by with no overcurrent fault
occurring, an even smaller amount of charge will be
removed from C
FLT
. If enough faults occur together,
eventually C
FLT
will charge up to 2.4 V and the fault latch
will be set. The fault latch will not be reset until the C
FLT
discharges to 0.6 V. This action will continue indefinitely if
the fault persists.
The off time and on time are set by the following:
Off Time C
FLT
2.4 V 0.6 V
4.5 A
On Time C
FLT
2.4 V 0.6 V
I
AVG
where:
I
AVG
(295.5 A DC) [4.5 A (1 DC)]
DC PWM Duty Cycle
I
AVG
(300 A DC) 4.5 A
Sleep State
This device will enter into a low current mode (< 275 µA)
when CTL lead is brought to less than 0.5 V. All functions
are disabled in this mode, except for the regulator.
Inhibit
When the inhibit voltage is greater than 2.5 V the internal
latch is set and the external MOSFET will be turned off for
the remainder of the oscillator cycle. The latch is then reset
at the start of the next cycle.
Overvoltage Shutdown
The IC will disable the output during an overvoltage
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is no undervoltage
lockout. The device will shutdown gracefully once it runs
out of headroom. This happens at the point when VREG falls
out of regulation.
Reverse Battery
The CS7054 will not survive a reverse battery condition.
Therefore, a series diode is required between the battery and
the V
CC
lead.
Load Dump
V
CC
is internally clamped to 30 V. It is recommended that
a 51 Ω resistor, (R
S
) is placed in series with V
CC
to limit the
current flow into the IC in the event of a 40 V peak transient
condition.
Using the CS7054 as a Frequency Converter
Figure 9 shows the CS7054 configured for use as a
frequency converter. In the setup shown, a 150 Hz square
wave from a microprocessor is converted to a 10 kHz square
wave. The duty cycle of each waveform is identical. The
amplitude of the input waveform is 5.0 V, but does not need
to be. The input amplitude requirement just needs to be high
enough to switch the external bipolar transistor. The 10 kHz
oscillator frequency is setup per the oscillator section of this
data sheet.
The external resistor divider composed of the 3.6 k and
6.2 k resistors supplies 5.0 V to the CTL pin when the input
duty cycle is at 100%. This also makes the output waveform
100%.
The RC filter (1.0 MΩ and 0.1 µF) sets up a pole at 1.6 Hz:
f
1
2RC
1
2
1M
(6.2 k)(3.6 k)
6.2 k3.6 k
(0.1 F)
1.6 Hz
In this case, the pole is 2 orders of magnitude below the
input waveform. Care must be taken to provide the
appropriate DC level on the control pin in addition to
providing the required response time.
*Note the current limit feature of the CS7054 has been
defeated by grounding the I
SENSE+
and the I
SENSE–
pins and
connecting the I
ADJ
lead to V
REG
.
