Data Sheet AD8340
L
V
L
NOR
S
P
AN 10MHz
1MHz/DIVCENTER 880MHz
–20
–40
–50
–60
–70
–80
–90
–100
110
MARKER 2 [T1 NOI]
–148.76dBm/Hz
876.009615385MHz
*RBW 30kHz
*VBW 30kHz
*SWT 100ms
*A
TT 5dB
BS, 1X, C0 : ADJ CHANNEL
REF –12dBm
04699-035
–30
CH PWR
AC
P LOW
ACP
U
P
ALT1 LOW
A
LT1 UP
–5.17dBm
–60.94dB
–60.08dB
–86.40dB
–86.80dB
MARKER 1 [T1 NOI]
–148.89dBm/Hz
884.006410256MHz
SWP 50 OF 50
2
OFFSET 0.5 dB
1
Figure 35. Output Spectrum, Single-Carrier CDMA2000 Test Model at −5 dBm
V
I
= V
Q
= 0.353 V, ACP Measured at 750 kHz and 1.98 MHz Carrier Offset,
Noise Measured at ±4 MHz Carrier Offset, Input Signal Filtered Using a
Cavity Tuned Filter (Pass Band = 4.6 MHz)
Holding the I and Q control voltages steady at 0.353 V, input
power was swept. Figure 36 shows the resulting output power,
noise floor, and adjacent channel power ratio. Noise floor is
presented as noise in a 1 MHz bandwidth as defined by the
3GPP2 specification.
04699-036
–30
–40
–50
–60
–70
–80
–90
–100
ACP – dBc (30kHz RBW)
–30 50–5–10–15–20–25
OUTPUT POWER (dBm)
–30
–90
–70
–60
–80
–50
–40
–100
NOISE – dBm @ 4MHz CARRIER OFFSET (1MHz RBW)
ACP – 750kHz OFFSET, 30kHz RBW
ACP – 1.98MHz OFFSET, 30kHz RBW
NOISE – 4MHz OFFSET, 1MHz RBW
Figure 36. Noise and ACP vs. Output Power,
Single-Carrier CDMA2000 Test Model, V
I
= V
Q
= 0.353,
ACP Measured in 30 kHz RBW at ±750 kHz and ±1.98 MHz Carrier Offset,
Noise Measured at ±4 MHz Carrier Offset
The results show that at an output power of 3 dBm, ACP is still
in compliance with the standard (<−45 dBc at 750 MHz and
<−60 dBc at 1.98 MHz). At low output power levels, ACP at
1.98 MHz, carrier offset degrades as the noise floor of the
AD8340 becomes the dominant contributor to measured ACP.
Measured noise at 4 MHz carrier offset begins to increase
sharply above 0 dBm output power. This increase is not due to noise.
but results from increased carrier-induced distortion. As output
power drops below 0 dBm, the noise floor drops towards −90 dBm.
With a fixed input power of 2.4 dBm, the output power was
again swept by exercising the I and Q inputs. V
I
and V
Q
were
kept equal and were swept from 10 mV to 500 mV. The
resulting output power, ACP, and noise floor are shown in
Figure 37.
04699-037
10
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dBm)
0 50 100 150 200 250 300
350 400 450 500
V
I
= V
Q
=V
IN
(mV)
–50
–55
–60
–65
–70
–75
–80
–85
–90
ACP – dBc (30kHz RBW)
NOISE – 4MHz CARRIER OFFSET – dBm (1MHz RBW)
P
OUT
vs. V
IN
ACP – 750kHz OFFSET, 30kHz RBW
NOISE – 4MHz OFFSET, 1MHz RBW
ACP – 1.98MHz OFFSET, 30kHz RBW
Figure 37. Output Power, Noise, and ACP vs. I and Q Control Voltages,
CDMA2000 Test Model, V
I
= V
Q
, ACP Measured in 30 kHz RBW at ±750 kHz
and ±1.98 MHz Carrier Offset, Noise Measured at ±4 MHz Carrier Offset
In contrast to Figure 36, Figure 37 shows that for a fixed input
power, ACP remains fairly constant as gain and phase are
changed (this is not true for very high input powers). The noise
floor still drops with decreasing gain, but it never reaches the
90 dBm level shown in Figure 37.
Figure 38 shows the output spectrum for a 3-carrier CDMA2000
spectrum. Again, the signal being applied to the AD8340 is
filtered by a cavity-tuned filter with a −3 dB bandwidth of
4.6 MHz. To reduce distortion, the total output carrier power
was reduced to approximately −8 dBm (per-carrier power =
−12.6 dBm). Adjacent channel power ratios of −61 dBc (2 MHz
from center of spectrum) and −82 dBc (3.23 MHz from center
of spectrum) were measured. The noise floor, measured at
5.25 MHz carrier offset, is approximately −149 dBm/Hz (−89 dBm
in a 1 MHz bandwidth). While some dynamic range is lost due
to output power back-off, ACP stays approximately equal and
noise floor improves slightly.
SOL
LVL
NOR
SPAN 15MHz1.5MHz/CENTER 880MHz
–20
–40
–50
–60
–70
–80
–90
–100
–110
*RBW 30kHz
*VBW 300kHz
*SWT 5s*ATT 5dB
REF –15 dBm
MARKER 1 [T1 NOI]
–148.83dBm/Hz
885.252403846MHz
OFFSET 0.5dB
1
04699-038
–30
CH1
CH2
CH3
TO
TAL
ACP LOW
ACP UP
ALT1 LOW
ALT1 UP
–12.65dBm
–12.58dB
–12.87dB
–7.93dB
–61.41dB
–61.87dB
–82.36dB
–81.92dB
A
Figure 38. Output Spectrum, 3-Carrier CDMA2000 Test Model at
12.5 dBm/Carrier, V
I
= V
Q
= 0.353 V, ACP Measured at 2 MHz and 3.23 kHz
Offset from Center of Spectrum, Noise Measured at 5.25 MHz Carrier Offset,
Input Signal Filtered Using a Cavity-Tuned Filter (Pass Band = 4.6 MHz)
Rev. C | Page 15 of 20
AD8340 Data Sheet
EVALUATION BOARD
The evaluation board circuit schematic for the AD8340 is
shown in Figure 39.
The evaluation board is configured to be driven from a
single-ended 50 Ω source. Although the input of the AD8340
is differential, it may be driven single-ended with no loss of
performance.
The low-pass corner frequency of the baseband I and Q
channels can be reduced by installing capacitors in the C11 and
C12 positions. The low-pass corner frequency for either
channel is approximated by
pF
5.
0
nF
10kHz
45
dB3
+
×
EXTERNAL
C
f
On the evaluation board, the I and Q baseband circuits are
identical, so the following description applies equally to each.
The connections and circuit configuration for the Q baseband
inputs are described in Table 4.
The baseband input of the AD8340 requires a differential
voltage drive. The evaluation board is set up to allow such a
drive by connecting the differential voltage source to QBBP and
QBBM. The common-mode voltage should be maintained at
approximately 0.5 V. For this configuration, Jumper W1 to
Jumper W4 should be removed.
The baseband input of the evaluation board can also be driven
with a single-ended voltage. In this case, a bias level is provided
to the unused input from Potentiometer R10 by installing either
W1 or W2.
Setting SW1 in Position B disables the AD8340 output
amplifier. With SW1 set to Position A, the output amplifier is
enabled and an external voltage signal, such as a pulse, can be
applied to the DSOP SMA connector to exercise the output
amplifier enable/disable function.
Rev. C | Page 16 of 20
Data Sheet AD8340
Table 4. Evaluation Board Configuration Options
Components Description Default Conditions
R7, R9, R11, R14,
R15, R19, R20, R21,
C15, C19, W3, W4
I Channel Baseband Interface. Resistor R7 and Resistor R9 can be
installed to accommodate a baseband source that requires a
specific terminating impedance. C15 and C19 are bypass
capacitors. For single-ended baseband drive, Potentiometer R11
can be used to provide a bias level to the unused input (install
either W3 or W4).
R7, R9 = open
R11 = potentiometer, 2 kΩ, 10 turns (Bourns)
R14 = 4 kΩ (Size 0603)
R15 = 44 kΩ (Size 0603)
R19, R20, R21 = 0 Ω (Size 0603)
C15, C19 = 0.1 µF (Size 0603)
W3 = jumper (installed)
W4 = jumper (open)
R1, R3, R10, R12,
R13, R16, R17, R18,
C16, C20, W1, W2
Q Channel Baseband Interface. See the I Channel Baseband
Interface description.
R1, R3 = open
R10 = potentiometer, 2 kΩ, 10 turns (Bourns)
R12 = 4 kΩ (Size 0603)
R13 = 44 kΩ (Size 0603)
R16, R17, R18 = 0 Ω (Size 0603)
C16, C20 = 0.1 µF (Size 0603)
W1 = jumper (installed)
W2 = jumper (open)
C11, C12
Baseband Low-Pass Filtering. By adding Capacitor C11 between
QFLP and QFLM, and Capacitor C12 between IFLP and IFLM, the
3 dB low-pass corner frequency of the baseband interface can be
reduced from 230 MHz (nominal). See the equation in the
Evaluation Board section.
C11, C12 = open
T1, C17, C18, L1, L2
Output Interface. The 1:1 balun transformer, T1, converts the 50 Ω
differential output to 50 Ω single-ended. C17 and C18 are dc
blocks. L1 and L2 provide dc bias for the output.
C17, C18 = 100 pF (Size 0603)
T1 = ETC1-1-13 (M/A-COM)
L1, L2 = 120 nH (Size 0603)
L3, L4, C5, C6
Input Interface. The input impedance of the AD8340 requires 5.6 nH
inductors in series with RFIP and RFIM for optimum return loss
when driven by a single-ended 50 Ω line. C5 and C6 are dc blocks.
L3, L4 = 5.6 nH (Size 0402)
C5, C6 = 100 pF (Size 0603)
C2, C4, C7, C9, C14,
C1, C3, C8, C10,
R2, R4, R5, R6
Supply Decoupling.
C2, C4, C7, C9 = open (Size 0603)
C1, C3, C8, C10, C14 = 0.1 µF (Size 0603)
R2, R4, R5, R6 = 0 Ω (Size 0603)
R8, SW1
Output Disable Interface. The output stage of the AD8340 is
disabled by applying a high voltage to the DSOP pin by moving
SW1 to Position B. The output stage is enabled by moving SW1 to
Position A. The output disable function can also be exercised by
applying an external high or low voltage to the DSOP SMA
connector with SW1 in Position A.
R8 = 10 kΩ (Size 0603)
SW1 = SPDT (Position A, output enabled)
Rev. C | Page 17 of 20

AD8340-EVALZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Development Tools RF VECTOR MODULATOR 700 - 1000MHz
Lifecycle:
New from this manufacturer.
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