Data Sheet AD8340
SPECIFICATIONS
V
S
= 5 V, T
A
= 25°C, Z
O
= 50 Ω, f = 880 MHz, single-ended, ac-coupled source drive to RFIP through 5.6 nH series inductor, RFIM
ac-coupled through 5.6 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1.
Parameter Conditions Min Typ Max Unit
Frequency Range 700 1000 MHz
Maximum Gain Maximum gain setpoint for all phase setpoints −2 dB
Minimum Gain V
BBI
= V
BBQ
= 0 V −32 dB
Gain Control Range Relative to maximum gain 30 dB
Phase Control Range Over 30 dB control range 360 Degrees
Gain Flatness Over any 60 MHz bandwidth 0.25 dB
Group Delay Flatness Over any 60 MHz bandwidth 10 ps
RFIM, RFIP (Pin 21 and Pin 22)
Input Return Loss From RFIP to CMRF (with 5.6 nH series inductors) 20 dB
CARTESIAN CONTROL INTERFACE (I and Q) IBBP, IBBM, QBBP, QBBM (Pin 16, Pin 15, Pin 3, Pin 4)
Modulation Bandwidth 250 mV p-p sinusoidal baseband input single-ended 230 MHz
Second Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 47 dBc
Third Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 45 dBc
Step Response
For gain setpoint from 0.1 to 0.9
(V
BBP
= 0.5 V, V
BBM
= 0.55 V to 0.95 V)
45 ns
For gain setpoint from 0.9 to 0.1
(V
BBP
= 0.5 V, V
BBM
= 0.95 V to 0.55 V)
RF OUTPUT STAGE RFOP, RFOM (Pin 9 and Pin 10)
Output Return Loss Measured through balun 7.5 dB
f = 880 MHz
Output Noise Floor Maximum gain setpoint, no input −149 dBm/Hz
P
IN
= 0 dBm, frequency offset = 20 MHz −147 dBm/Hz
Output IP3 f1 = 880 MHz, f2 = 877.5 MHz, maximum gain setpoint 24 dBm
ACPR
IS-95, single carrier, P
OUT
= 0 dBm, maximum gain,
phase setpoint = 45°
62 dBc
Output 1 dB Compression Point
POWER SUPPLY VPS2 (Pin 5, Pin 6, Pin 14); RFOP, RFOM (Pin 9 and Pin 10)
Positive Supply Voltage 4.75 5 5.25 V
Total Supply Current Includes load current 110 130 150 mA
OUTPUT DISABLE DSOP (Pin 13)
Disable Threshold 2.5 V
Maximum Attenuation DSOP = 5 V 40 dB
Enable Response Time
Delay following high-to-low transition until device
meets full specifications
15 ns
Disable Response Time
Delay following low-to-high transition until device
produces full attenuation
10 ns
Rev. C | Page 3 of 20
