PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF36C256_512x72.fm - Rev. C 1/07 EN
13 ©2005 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
Table 14: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage
VDDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs
VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA
VOL –0.4V
Input leakage current: VIN = GND to VDD
ILI 0.10 3 µA
Output leakage current: V
OUT = GND to VDD
ILO 0.05 3 µA
Standby current
ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 KHz
ICC
R
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 KHz
I
CC
W
23mA
Table 15: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F–300ns2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 µs
SDA and SCL rise time
t
R–0.3µs2
SCL clock frequency
f
SCL 400 KHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF36C256_512x72.fm - Rev. C 1/07 EN
14 ©2005 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Table 16: Serial Presence-Detect Matrix
Byte Description Entry (Version) 2GB 4GB
0
Number of SPD bytes used by Micron
128 80 80
1
Total number of bytes in SPD device
256 08 08
2
Fundamental memory type
DDR2 SDRAM 08 08
3
Number of row addresses on SDRAM
14 0E 0E
4
Number of column addresses on SDRAM
11 0B 0B
5
DIMM height and module ranks
30mm, dual rank 61 61
6
Module data width
72 48 48
7
Reserved
00000
8
Module voltage interface levels
SSTL 1.8V 05 05
9
SDRAM cycle time,
t
CK
(CL = MAX value, see byte 18)
-80E
-800
-667
-53E
-40E
25
25
30
3D
50
25
25
30
3D
50
10
SDRAM access from clock,
t
AC
(CL = MAX value, see byte 18)
-80E/-800
-667
-53E
-40E
40
45
50
60
40
45
50
60
11
Module configuration type
ECC
ECC and parity (P)
02
06
02
06
12
Refresh rate/type
7.81µs/SELF 82 82
13
SDRAM device width (primary SDRAM)
40404
14
Error-checking SDRAM data width
40404
15
Reserved
00 00
16
Burst lengths supported
4, 8 0C 0C
17
Number of banks on SDRAM device
4 or 8 04 08
18
CAS latencies supported
-80E (5, 4)
-800 (6, 5,4)
-667 (5, 4, 3)
-53E/-40E (4, 3)
30
70
38
18
30
70
38
18
19
Module thickness
–0101
20
DDR2 DIMM type
Registered DIMM 01 01
21
SDRAM module attributes
1 PLL, 2 registers
1 PLL, 4 registers
07
05
22
SDRAM device attributes: weak driver (01) or, weak
driver and 50Ω ODT (03)
-80E/-800/-667
-53E/-40E
03
01
03
01
23
SDRAM cycle time,
t
CK, MAX CL - 1
-80E/-667
-800
-53E/-40E
3D
30
50
3D
30
50
24
SDRAM access from CK,
t
AC, MAX CL - 1
-80E/-800
-667
-53E
-40E
40
45
50
60
40
45
50
60
25
SDRAM cycle time,
t
CK, MAX CL - 2
-80E/-800
-667
-53E/-40E
00/3D
50
00
00/3D
50
00
PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF36C256_512x72.fm - Rev. C 1/07 EN
15 ©2005 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
26
SDRAM access from CK,
t
AC, MAX CL - 2
-80E/-800
-667
-53E/-40E
00/40
45
00
00/40
45
00
27
MIN row precharge time,
t
RP
-80E
-800/-667
-53E/-40E
32
3C
3C
32
3C
3C
28
MIN row active-to-row active,
t
RRD
1E 1E
29
MIN RAS#-to-CAS# delay,
t
RCD
-80E
-800/-667
-53E/-40E
32
3C
3C
32
3C
3C
30
MIN active-to-precharge time,
t
RAS
-800/-80E
-667/-53E
-40E
2D
2D
28
2D
2D
28
31
Module rank density
2GB, 4GB 01 02
32
Address and command setup time,
t
IS
b
-80E/-800
-667
-53E
-40E
17
20
25
35
17
20
25
35
33
Address and command hold time,
t
IH
b
-80E/-800
-667
-53E
-40E
25
27
37
47
25
27
37
47
34
Data/data mask input setup time,
t
DS
b
-80E/-800
-667/-53E
-40E
05
10
15
05
10
15
35
Data/data mask input hold time,
t
DH
b
-80E/-800
-667
-53E
-40E
12
17
22
27
12
17
22
27
36
Write recovery time,
t
WR
3C 3C
37
WRITE-to-READ command delay,
t
WTR
-80E/-667/-53E
-800/-40E
1E
28
1E
28
38
READ-to-PRECHARGE command delay,
t
RTP
1E 1E
39
Memory analysis probe
00 00
40
Extension for bytes 41 and 42
-80E
-800/-667
-53E/-40E
30
00
00
36
06
06
41
MIN active-to-active/refresh time,
t
RC
1
-80E
-800/-667/-53E
-40E
39
3C
37
39
3C
37
42
MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH
command period,
t
RFC
69 7F
43
SDRAM device MAX cycle time,
t
CK (MAX)
80 80
44
SDRAM device MAX DQS–DQ skew time,
t
DQSQ
-80E/-800
-667
-53E
-40E
14
18
1E
23
14
18
1E
23
Table 16: Serial Presence-Detect Matrix (continued)
Byte Description Entry (Version) 2GB 4GB

MT36HTF25672Y-667D1

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 2GB 240RDIMM
Lifecycle:
New from this manufacturer.
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