PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF36C256_512x72.fm - Rev. C 1/07 EN
13 ©2005 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
Table 14: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage
VDDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs
VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA
VOL –0.4V
Input leakage current: VIN = GND to VDD
ILI 0.10 3 µA
Output leakage current: V
OUT = GND to VDD
ILO 0.05 3 µA
Standby current
ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 KHz
ICC
R
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 KHz
I
CC
W
23mA
Table 15: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F–300ns2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 – µs
SDA and SCL rise time
t
R–0.3µs2
SCL clock frequency
f
SCL – 400 KHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
