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89H32NT24BG2ZAHL8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
IDT 89HPES32NT24BG2 Datasheet
19 of 37 December 17, 2013
Figure 5 JTAG AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 — ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 — ns
Thld_16b 1.0 — ns
JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 — ns
Table 14 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
IDT 89HPES32NT24BG2 Datasheet
20 of 37 December 17, 2013
Recommended Operating Temperature
Recommended Operating Supply Voltages — Commercial Temperature
Recommended Operating Supply Voltages — Industrial Temperature
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Grade Temperature
Commercial 0C to +70C Ambient
Industrial -40C to +85C Ambient
Table 15 PES32NT24BG2 Operating Temperatures
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 16 PES32NT24BG2 Operating Voltages — Commercial Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.05 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 17 PES32NT24BG2 Operating Voltages — Industrial Temperature
IDT 89HPES32NT24BG2 Datasheet
21 of 37 December 17, 2013
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 16 (and also listed below).
Note 1: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in V
DD
PEA, V
DD
PEHA, and
V
DD
PETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned-
off port is close to zero. For example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 3/16 multiplied by the power consumption indicated in the above table.
Note 2: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: V
DD
PEA, V
DD
PEHA, and
V
DD
PETA.
Thermal Considerations
This section describes thermal considerations for the PES32NT24BG2 (23mm
2
FCBGA484 package). The data in Table 19 below contains infor-
mation that is relevant to the thermal performance of the PES32NT24BG2 switch.
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465
Typ
Power
Max
Power
x8/x8/x8/x4/x4
(Full Swing)
mA 2535 3400 1627 1855 233 233 687 740 3 5
Watts 2.54 3.74 1.63 2.04 0.58 0.64 0.69 0.81 0.01 0.02 5.45 7.25
x8/x8/x8/x4/x4
(Half Swing)
mA 2535 3400 1399 1595 233 233 357 385 3 5
Watts 2.54 3.74 1.40 1.76 0.58 0.64 0.36 0.42 0.01 .02 4.89 6.58
Table 18 PES32NT24BG2 Power Consumption
Symbol Parameter Value Units Conditions
T
J(max)
Junction Temperature 125
o
CMaximum
T
A(max)
Ambient Temperature 70
o
C Maximum for commercial-rated products
85
o
C Maximum for industrial-rated products
JA(effective)
Effective Thermal Resistance, Junction-to-Ambient
15.2
o
C/W Zero air flow
8.5
o
C/W 1 m/S air flow
7.1
o
C/W 2 m/S air flow
JB
Thermal Resistance, Junction-to-Board 3.1
o
C/W
JC
Thermal Resistance, Junction-to-Case 0.15
o
C/W
P Power Dissipation of the Device 7.25 Watts Maximum
Table 19 Thermal Specifications for PES32NT24BG2, 23x23 mm FCBGA484 Package
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

89H32NT24BG2ZAHL8

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Buy 89H32NT24BG2ZAHL8
Manufacturer:
IDT
Description:
PCI Interface IC
Lifecycle:
New from this manufacturer.
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