IDT 89HPES32NT24BG2 Datasheet
25 of 37 December 17, 2013
Absolute Maximum Voltage Rating
Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages
in Table 16. The absolute maximum operating voltages in Table 21 are offered to provide guidelines for voltage excursions outside the recommended
voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside
the maximum range may adversely affect device functionality and reliability.
SMBus Characterization
Capacitance C
IN
8.5 8.5 pF
Leakage Inputs + 10 + 10 AV
DD
I/O (max)
I/O
LEAK W/O
Pull-ups/downs
——+ 10 + 10 AV
DD
I/O (max)
I/O
LEAK WITH
Pull-ups/downs
——+ 80 + 80 AV
DD
I/O (max)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1.
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply
1.5V 1.5V 4.6V 1.5V 4.6V
Table 21 PES32NT24BG2 Absolute Maximum Voltage Rating
Symbol Parameter
SMBus 2.0 Char. Data
1
Unit
3V 3.3V 3.6V
DC Parameter for SDA Pin
V
IL
Input Low 1.16 1.26 1.35 V
V
IH
Input High 1.56 1.67 1.78 V
V
OL@350uA
Output Low 15 15 15 mV
I
OL@0.4V
23 24 25 mA
I
Pullup
Current Source A
I
IL_Leak
Input Low Leakage 0 0 0 A
I
IH_Leak
Input High Leakage 0 0 0 A
Table 22 SMBus DC Characterization Data (Part 1 of 2)
I/O Type Parameter Description
Gen1 Gen2 Unit
Condi-
tions
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
Table 20 DC Electrical Characteristics (Part 3 of 3)
IDT 89HPES32NT24BG2 Datasheet
26 of 37 December 17, 2013
DC Parameter for SCL Pin
V
IL (V)
Input Low 1.11 1.2 1.31 V
V
IH (V)
Input High 1.54 1.65 1.76 V
I
IL_Leak
Input Low Leakage 0 0 0 A
I
IH_Leak
Input High Leakage 0 0 0 A
1.
Data at room and hot temperature.
Symbol Parameter
SMBus @3.3V ±10%
1
1.
Data at room and hot temperature.
Unit
Min Max
F
SCL
Clock frequency 5 600 KHz
T
BUF
Bus free time between Stop and
Start
3.5 s
T
HD:STA
Start condition hold time 1 s
T
SU:STA
Start condition setup time 1 s
T
SU:STO
Stop condition setup time 1 s
T
HD:DAT
Data hold time 1 ns
T
SU:DAT
Data setup time 1 ns
T
TIMEOUT
Detect clock low time out 74.7 ms
T
LOW
2
2.
T
LOW
and
T
HIGH
are measured at F
SCL
= 135 kHz.
Clock low period 3.7 s
T
HIGH
2
Clock high period 3.7 s
T
F
Clock/Data fall time 72.2 ns
T
R
Clock/Data rise time 68.3 ns
T
POR@10kHz
Time which a device must be
operational after power-on reset
20 ms
Table 23 SMBus AC Timing Data
Symbol Parameter
SMBus 2.0 Char. Data
1
Unit
3V 3.3V 3.6V
Table 22 SMBus DC Characterization Data (Part 2 of 2)
IDT 89HPES32NT24BG2 Datasheet
27 of 37 December 17, 2013
Package Pinout — 484-BGA Signal Pinout for the PES32NT24BG2
The following table lists the pin numbers and signal names for the PES32NT24BG2 device. Note: Pins labeled NC are No Connection.
Pin Function Alt. Pin Function Alt. Pin Function Alt.
A1 STK2CFG1 B5 V
SS
C9 V
SS
A2 V
DD
I/O B6 PE06TN1 C10 PE06RN0
A3 PE07TP1 B7 PE06TN0 C11 V
SS
A4 PE07TP0 B8 V
SS
C12 V
SS
A5 V
SS
B9 GCLKN0 C13 PE05RN1
A6 PE06TP1 B10 V
SS
C14 V
SS
A7 PE06TP0 B11 PE05TN1 C15 PE05RN0
A8 V
SS
B12 PE05TN0 C16 REFRES02
A9 GCLKP0 B13 V
SS
C17 V
SS
A10 V
SS
B14 P04CLKN C18 PE04RN0
A11 PE05TP1 B15 V
SS
C19 PERSTN
A12 PE05TP0 B16 PE04TN1 C20 JTAG_TRST_N
A13 V
SS
B17 PE04TN0 C21 SSMBDAT
A14 P04CLKP B18 V
DD
I/O C22 V
DD
I/O
A15 V
SS
B19 MSMBCLK D1 STK2CFG4
A16 PE04TP1 B20 JTAG_TMS D2 V
DD
I/O
A17 PE04TP0 B21 SSMBCLK D3 V
SS
A18 V
DD
I/O B22 JTAG_TCK D4 STK3CFG4
A19 MSMBDAT C1 STK2CFG3 D5 PE07RP1
A20 JTAG_TDO C2 V
DD
I/O D6 PE07RN0
A21 CLKMODE1 C3 V
SS
D7 V
SS
A22 SSMBADDR2 C4 STK3CFG3 D8 PE06RP1
B1 STK2CFG2 C5 PE07RN1 D9 V
SS
B2 V
DD
I/O C6 V
SS
D10 PE06RP0
B3 PE07TN1 C7 V
SS
D11 REFRESPLL
B4 PE07TN0 C8 PE06RN1 D12 V
SS
Table 24 PES 32NT24BG2 Signal Pin-Out (Part 1 of 7)

89H32NT24BG2ZAHL8

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC
Lifecycle:
New from this manufacturer.
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