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71016S15PHGI

P1-P3P4-P6P7-P9
6.42
4
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
Figure 3. Output Capacitive Derating
AC Test Loads
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160
180
200
Δt
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3210 drw 05
•
•
•
•
•
•
•
,
3210 drw 04
480Ω
255Ω5pF*
DATA
OUT
5V
,
480Ω
255Ω30pF*
DATA
OUT
5V
3210 drw 03
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3210 tbl 09
6.42
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)
DATA
OUT
ADDRESS
3210 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
,
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 12ns commercial only.
71016S12
(2)
71016S15 71016S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 12
____
15
____
20
____
ns
t
AA
Address Access Time
____
12
____
15
____
20 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20 ns
t
CLZ
(1)
Chip Select Low to Output in Low-Z 4
____
5
____
5
____
ns
t
CHZ
(1)
Chip Select High to Output in High-Z
____
6
____
6
____
8ns
t
OE
Output Enable Low to Output Valid
____
7
____
8
____
10 ns
t
OLZ
(1)
Output Enable Low to Output in Low-Z 0
____
0
____
0
____
ns
t
OHZ
(1)
Output Enable High to Output in High-Z
____
6
____
6
____
8ns
t
OH
Output Hold from Address Change 4
____
4
____
5
____
ns
t
BE
Byte Enable Low to Output Valid
____
7
____
8
____
10 ns
t
BLZ
(1)
Byte Enable Low to Output in Low-Z 0
____
0
____
0
____
ns
t
BHZ
(1)
Byte Enable High to Output in High-Z
____
6
____
6
____
8ns
WRITE CYCLE
t
WC
Write Cycle Time 12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write 9
____
10
____
12
____
ns
t
CW
Chip Select Low to End of Write 9
____
10
____
12
____
ns
t
BW
Byte Enable Low to End of Write 9
____
10
____
12
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 9
____
10
____
12
____
ns
t
DW
Data Valid to End of Write 7
____
8
____
10
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
ns
t
OW
(1)
Write Enable High to Output in Low-Z 1
____
1
____
1
____
ns
t
WHZ
(1)
Write Enable Low to Output in High-Z
____
6
____
6
____
8ns
3210 tbl 10
6.42
6
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2
(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
DATA
OUT
3210 drw 07
(3)
(3)
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
,
OE
CS
BHE, BL E
ADDRESS
CS
DATA
IN
3210 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
,
P1-P3P4-P6P7-P9

71016S15PHGI

Mfr. #:
Buy 71016S15PHGI
Manufacturer:
IDT
Description:
SRAM 64Kx16 ASYNCHRONOUS 5.0V STATIC RAM
Lifecycle:
New from this manufacturer.
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