LTC4260CGN#PBF Datasheet LTC4260IGN#PBF, LTC4260CGN#PBF, LTC4260CUH#PBF | P13-P15

LTC4260

4260fc

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applicaTions inForMaTion

As the SOURCE voltage rises, so will the FB pin which

is monitoring it. If the voltage across the current sense

resistor R

gets too high, the inrush current will then be

limited by the internal current limit circuitry. Once the FB

pin crosses its 3.5V threshold, the GPIO pin, in its default

configuration, will cease to pull low and indicate that the

power is now good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions.

A normal turn-off is initiated by the ON pin going low or

a serial bus turn-off command. Additionally, several fault

conditions will turn off the switch. These include an input

overvoltage (OV pin), input undervoltage (UV pin), over-

current circuit breaker (SENSE pin) or BDPRST going

high. Writing a logic one into the UV, OV or overcurrent

fault bits will also turn off the switch if their autoretry bits

are set to false.

Normally the switch is turned off with a 1mA current pulling

down the GATE pin to ground. With the switch turned off,

the SOURCE voltage drops and when the FB pin crosses

below its threshold, GPIO pulls low to indicate that the

output

power is no longer good.

If the

pin falls below 7.5V for greater than 5µs or INTV

drops below 3.8V for greater than 1µs, a fast shutdown of

the switch is initiated. The GATE pin is pulled down with

a 600mA current to the SOURCE pin.

+ 13V

4260 F02

GATE

OUT

SLOPE = 18µA/C1

Figure 2. Supply Turn-On

Overcurrent Fault

The LTC4260 features an adjustable current limit with fold-

back that protects against short circuits or excessive load

current. To protect against excessive power dissipation in

the switch during active current limit, the available current

is reduced as a function of the output voltage sensed by

the FB pin. The device also features a variable overcurrent

response time. A graph in the Typical Performance curves

shows the delay from a voltage step at the SENSE pin until

the GATE voltage starts falling, as a function of overdrive.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set by

the TIMER pin. Current limiting begins when the current

sense voltage between the V

and SENSE pins reaches

20mV to 50mV (depending on the foldback). The GATE

pin is then brought down with a 600mA GATE-to-SOURCE

current. The voltage on the GATE is regulated in order

to limit the current sense voltage to less than 50mV. At

this point, a circuit breaker time delay starts by charging

the external timing capacitor from the TIMER pin with a

100µA pull-up current. If the

TIMER pin reaches its 1.2V

threshold,

the external switch turns off (with a 1mA cur-

rent from GATE to ground). The overcurrent present bit,

C2, and the overcurrent fault bit, D2, are set at this time.

The circuit breaker time delay is given by:

= C

• 12 [ms/µF]

After the switch is turned off, the TIMER pin begins

discharging the timing capacitor with a 2µA pull-down

current. When the TIMER pin reaches its 0.2V threshold,

the overcurrent present bit, C2, is cleared, and the switch

will be allowed to turn on again if the overcurrent fault has

been cleared. However, if the overcurrent autoretry bit, A2,

has been set then the switch turns on again automatically

(without resetting the overcurrent fault). Use a minimum

value of 0.1nF for C

The waveform in Figure 3 shows how the output latches

off following a short circuit. The drop across the sense

resistor is held at 20mV as the timer ramps up.

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During a short circuit, if the current limit sense voltage

exceeds 150mV, the active current limit enters a high cur-

rent protection mode that immediately turns off the output

transistor by pulling the GATE-to-SOURCE voltage to zero.

Current in the output transistor drops from tens of amps

to zero in a few hundred nanoseconds. The input voltage

will drop during the high current and then spike upwards

due to parasitic inductances when the FET shuts off (see

Supply Transients). Following this event, the part may turn

on again after a delay (typically the 100ms normal turn-on

delay if the input voltage drops below the UVLO threshold)

and enters active current limit before shutting off.

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above

its 3.5V threshold. This shuts off the switch immediately

(with a 1mA current from GATE to ground) and sets the

overvoltage present bit, C0, and the overvoltage fault

bit D0. If the OV pin subsequently falls back below the

threshold for 100ms, the switch will be allowed to turn on

again unless the overvoltage autoretry has been disabled

by clearing bit A0.

Undervoltage Fault

An undervoltage fault occurs when the

UV pin falls below

its

3.12V threshold. This turns off the switch immediately

(with a 1mA current from GATE to ground) and sets the

undervoltage present bit, C1, and the undervoltage fault

bit D1. If the UV pin subsequently rises above the thresh-

old for 100ms, the switch will turn on again unless the

applicaTions inForMaTion

OUT

50V/DIV

OUT

5A/DIV

∆V

GATE

10V/DIV

TIMER

2V/DIV

100µs/DIV

4260 F03

Figure 3. Short-Circuit Waveforms

undervoltage autoretry has been disabled by clearing bit

A1. When power is applied to the device, if UV is below its

3.12V threshold after INTV

crosses its 4.5V undervoltage

lockout threshold, an undervoltage fault will be logged in

the fault register.

Board Present Change of State

Whenever the BDPRST pin toggles, bit D4 is set to

indicate a change of state. When the BDPRST pin goes

high, indicating board removal, the switch turns off im-

mediately (with a 1mA current from GATE to ground) and

clears the board present bit, C4. If the BDPRST pin is

pulled low, indicating a board insertion, all fault bits except

D4 will be cleared and the board present bit, C4, is set. If

the BDPRST pin remains low for 100ms the state of the

ON pin will be captured in the FET On Control bit A3. This

turns the switch on if the ON pin is tied high. There is an

internal 10µA pull-up current source on the BDPRST pin.

If the system shuts down due to a fault, it may be desirable

to restart the system simply by removing and reinserting

a load card. In cases where

the LTC4260 and the switch

reside

on a backplane or midplane and the load resides

on a plug-in card, the BDPRST pin can be used to detect

when the plug-in card is removed (see Figure 4). Once

the plug-in card is reinserted the fault register is cleared

(except for D4). After 100ms the state of the ON pin is

latched into bit A3 of the control register. At this point the

system will start up again.

If a connection sense on the plug-in card is driving the

BDPRST

pin, the insertion or removal of the card may

cause the pin voltage to bounce. This will result in clear-

ing the fault register when the card is removed. The pin

can be debounced using a filter capacitor, C

BDPRST

, on

the

BDPRST

pin as shown in Figure 4. The filter time

is given by:

FILTER

BDPRST

• 123 [ms/µF]

FET Short Fault

A FET short fault will be reported if the data converter

measures a current sense voltage greater than or equal

to 2mV while the FET is turned off. This condition sets the

FET short present bit, C5, and the FET short

fault bit D5.

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Power Bad Present/Power Bad Fault

When the FB pin drops below its 3.41V threshold the

power bad present bit, C3, goes high. This pulls the GPIO

pin low immediately when configured as PWRGD. If the

FB pin subsequently rises back above the threshold, the

GPIO pin will return to a high impedance state and bit C3

will be cleared.

The power bad fault bit, D3, is set when the GATE-to-

SOURCE voltage is high and the power bad present C3

bit is high. This blanking with the gate voltage prevents

false power bad faults during power-up or power-down.

Fault Alerts

When any of the fault bits in FAULT register D are set,

an optional I

C bus alert can be generated by setting the

appropriate bit in the ALERT register B. This allows only

selected faults to generate alerts. At power-up the default

state is to not alert on faults. If an alert is enabled, the cor-

responding fault will cause the ALERT pin to pull low. After

the bus master controller broadcasts the Alert Response

Address, the LTC4260 responds with its address on the

SDA line and releases ALERT as shown in

Figure 11.

there is a collision between two LTC4260s responding

with their addresses simultaneously, then the device with

the lower address wins arbitration and responds first. The

ALERT line will also be released if the device is addressed

by the bus master.

–

1.235V

GND

MOTHERBOARD

CONNECTOR PLUG-IN

CARD

SOURCE

OUT

LTC4260

10µA

BD_PRST 14

BD_PRST

LOAD

4260 F04

Figure 4. Plug-In Card Insertion/Removal

Once the ALERT signal has been released for one fault,

it will not be pulled low again until the FAULT register

indicates a different fault has occurred or the original

fault is cleared and it occurs again. Note that this means

repeated or continuing faults will not generate alerts until

the associated FAULT register bit has been cleared.

Resetting Faults

Faults are reset with any of the following conditions. First,

a serial bus command writing zeros to the FAULT register

D will clear the associated faults. Second, the entire FAULT

the ON pin or bit A3 going from high to low, or if the UV

pin is brought below its 1.23V reset threshold, or if INTV

falls below its 3.8V undervoltage lockout threshold. Finally,

when BDPRST is brought from high to low, only FAULT

bits D0-D3 and D5 are cleared, the bit D4 that indicates a

BDPRST change of state will be set. Faults that are still

present (as indicated in the STATUS Register C) cannot

be cleared.

The FAULT register will not be cleared when autoretrying.

When autoretry is disabled the existence of a D0,

D1 or D2

fault

keeps the switch off. As soon as the fault is cleared,

the switch will turn on. If autoretry is enabled, then a high

value in C0, C1 or C2 will hold the switch off and the FAULT

C2 bits are cleared, the switch is allowed to turn on again.

Data Converter

The LTC4260 incorporates an 8-bit data converter that

continuously monitors three different voltages. The Δ∑

architecture inherently averages signal noise during the

measurement period. The SOURCE pin uses a 1/40 resis-

tive divider to monitor a full-scale voltage of 102.4V with

0.4V resolution (divider converts 102.4V to 2.56V). The

ADIN pin is monitored with a 2.56V full scale and 10mV

resolution, and the voltage between the V

and SENSE

pins is monitored with a 76.8mV full scale and 300µV

resolution.

The results from each conversion are stored in registers

E, F and G and are updated 10 times per second. Setting

CONTROL register bit A5 invokes a test mode that halts

the data converter updates so that registers E, F and G

can be written to and read from for software testing.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

LTC4260CGN#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Hot Swap Voltage Controllers 48V Hot Swap Controller with I2C ADC

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LTC4260CGN#PBF

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