LTC4260
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applicaTions inForMaTion
Gate Pin Voltage
A curve of gate drive vs V
DD
is shown in the Typical Per-
formance curves. At the minimum input supply voltage
of 8.5V, the minimum gate drive voltage is 4.5V. When
the input supply voltage is higher than 20V, the gate
drive is at least 10V and a regular N-FET can be used. In
applications over a 8.5V to 20V range, a logic level N-FET
must be used to maintain adequate gate enhancement.
The GATE pin is clamped at a typical value of 15V above
the SOURCE pin.
Configuring the GPIO Pin
Table 3 describes the possible states of the GPIO pin us-
ing the control register bits A6 and A7. At power-up, the
default state is for the GPIO pin to go high impedance
when power is good (FB pin greater than 3.5V). Other uses
for the GPIO pin are to pull down when power is good,
a general purpose output and a general purpose input.
Compensating the Active Current Loop
The active current limit circuit is compensated using the
resistor R6 and the slew rate capacitor C1. The value for
C1 is calculated to limit the inrush current. The suggested
value for R6 is 100k. This value should work for most pass
FETs (Q1). If the gate capacitance of Q1 is very small then
the best method to compensate the loop is to add a ≈10nF
capacitor between the GATE and SOURCE terminals.The
addition of 10Ω resistor (R5) prevents self-oscillation in
Q1 by isolating trace capacitance from the FET's GATE
Terminal. Locate the gate resistor at, or close to, the body
of the MOSFET.
Supply Transients
The LTC4260 is designed to ride through supply transients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5µH, there is a chance that the supply could collapse
before the active current limit circuit brings down the
GATE pin. In this case the undervoltage monitors turn
off the pass FET. The undervoltage lockout circuit has a
5µs filter time after V
DD
drops below 7.5V. The UV pin
reacts ins to shut the GATE off, but it is recommended
to add a filter capacitor C
F
to prevent unwanted shutdown
caused by short transient. Eventually either the UV pin or
the undervoltage lockout responds to bring the current
under control before the supply completely collapses.
Supply T
ransient Protection
The LTC4260 is 100% tested and guaranteed to be safe from
damage with supply voltages up to 100V. However, spikes
above 100V may damage the part. During a short-circuit
condition, the large change in currents flowing through the
power supply traces can cause inductive voltage spikes
which could exceed 100V. To minimize the spikes, the
power trace inductance should be minimized by using
wider traces or heavier trace plating. Adding a snubber
circuit will dampen the voltage spikes. It is built using a
100Ω resistor in series with a 0.1µF capacitor between
V
DD
and GND. A surge suppressor, Z1 in Figure 1, at the
input will clamp the voltage spikes.
Design Example
As a design example, take the following specifications:
V
IN
= 48V, I
MAX
= 5A, I
INRUSH
= 1A, C
L
= 330µF, V
UVON
= 43V, V
UVOFF
= 38.5V, V
OVOFF
= 70V, V
PWRGDUP
= 46V,
V
PWRGDDN
= 45V and I
2
C
ADDRESS
= 1010011. The selec-
tion of the sense resistor, R
S
, is set by the overcurrent
threshold of 50mV:
R
S
=
50mV
I
MAX
=
50mV
5A
= 0.010
The FET should be sized to handle the power dissipation
during the inrush charging of the output capacitor C
OUT
.
The method used to determine the power is the principle:
E
C
= Energy in C
L
= Energy in Q1
Thus:
E
C
= 1/2 CV
2
= 1/2(0.33mF)(48V)
2
= 0.38J
Calculate the time it takes to charge up C
OUT
:
t
CHARGUP
=
C
L
V
IN
I
INRUSH
=
330µF 48V
1A
= 16ms
The average power dissipated in the FET:
P
DISS
=
E
C
t
CHARGUP
=
0.38J
16ms
24W
LTC4260
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applicaTions inForMaTion
The SOA (safe operating area) curves of candidate FETs
must be evaluated to ensure that the heat capacity of the
package can stand 24W for 16ms. The SOA curves of the
Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms,
satisfying the requirement.
The inrush current is set to 1A using C1:
C1= C
L
I
GATE(UP)
I
INRUSH
= 0.33mF
18µA
1A
= 5.9nF
Default values of R5 = 10Ω and R6 = 100k are chosen as
discussed previously.
The power dissipated in the FET during overcurrent must
be limited. The active current limit uses a timer to prevent
excessive energy dissipation in the FET. The worst-case
power occurs when the voltage versus current profile of
the foldback current limit is at the maximum. This occurs
when the current is 5A and the voltage is 1/2 of the 48V
or 24V. See the Current Limit Sense Voltage vs FB Voltage
in the Typical Performance curves to view this profile. In
order to survive 120W, the FET SOA curve dictates the
maximum time at this power level. This particular FET
allows 300W at 1ms or less. Therefore, it is acceptable
to set the current limit timeout using C
T
to be 0.81ms:
C
T
=
0.81ms
12 ms/µF
[ ]
= 68nF
Note the minimum value for C
T
is 0.1nF.
Choose R1, R2, R3, R7 and R8 for the UV, OV and PG
threshold voltages:
V
OVRISING
= 71.2V, V
OVFALLING
= 69.44V (using V
OV(TH)
=
3.5V rising and 3.41V falling)
V
UVRISING
= 43V, V
UVFALLING
= 38.5V, (using V
UV(TH)
=
3.5V rising and 3.12V falling)
V
PGRISING
= 46.14V, V
PGFALLING
= 45V, (using V
FB
= 3.5V
rising and 3.411V falling)
In addition a 0.1µF ceramic bypass capacitor is placed on
the INTV
CC
pin. The complete circuit is shown in Figure 1.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02” per amp to make sure the trace stays at
a reasonable temperature. Using 0.03” per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/square. Small resistances add
up quickly in high current applications. To improve noise
immunity, put the resistive divider to the UV, OV and FB
pins close to the device and keep traces to V
DD
and GND
short. It is also important to put C3, the bypass capacitor
for the INTV
CC
pin, as close as possible between INTV
CC
and GND. A 0.1µF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 5 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
SENSE
LTC4260
V
DD
UV
R1
SENSE RESISTOR R
S
I
LOAD
V
IN
GND
I
LOAD
R2
R3
R
8
C3
4260 F05
C
F
OV
GND INTV
CC
FB
Z1
Figure 5. Recommended Layout for
R1, R2, R3, R8, C
F
, C3, Z1 and R
S
LTC4260
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Digital Interface
The LTC4260 communicates with a bus master using
a 2-wire interface compatible with the I
2
C bus and the
SMBus, an I
2
C extension for low power devices.
The LTC4260 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word com-
mand will be identical to the first word. The second word
in a Write Word command is ignored. The data formats
for these commands are shown in Figures 6 to 10.
Using Optoisolators with SDA
The LTC4260 separates the SDA line into SDAI and SDAO.
If optoisolators are not used then tie SDAI and SDAO
together to construct a normal SDA line. When using
optoisolators connect the SDAI to the output of the incom-
ing opto and connect the SDAO to the input of the out-
going opto (see Figure 13).
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high
(Figure 6). A bus master signals the beginning of a
transmission with a START condition by transitioning SDA
from high to low while SCL is high. When the master has
finished communicating with
the slave, it issues a STOP
condition
by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
I
2
C Device Addressing
Twenty-seven distinct bus address are configurable us-
ing the three-state ADR0-ADR2 pins. Table 1 shows the
correspondence between pin states and addresses. Note
that address bits B7 and B6 are internally configured to
10. In addition, the LTC4260 will respond to two special
addresses. Address (1011 111)b is a mass write used to
write to all LTC4260, regardless of their individual address
settings. The mass write can be masked by setting register
bit A4 to zero. Address (0001 100)b is the SMBus Alert
Response Address. If the LTC4260 is pulling low on the
ALERT pin, it will acknowledge this address using the
SMBus Alert Response Protocol.
applicaTions inForMaTion
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last byte
of data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it must pull down the SDA line so that
it remains LOW during this pulse to acknowledge receipt
of the data
. If the slave fails to acknowledge by leaving
SDA
HIGH, then the master can abort the transmission by
generating a STOP condition. When the master is receiving
data from the slave, the master must pull down the SDA
line during the clock pulse to indicate receipt of the data.
After the last byte has been received the master will leave
the SDA line HIGH (not acknowledge) and issue a STOP
condition to terminate the transmission.
Write Protocol
The master begins communication with a START condition
followed by the seven bit slave address and the R/W bit set
to zero (Figure 7). The addressed LTC4260 acknowledges
this and then the master sends a command byte which
indicates which internal register the master wishes to write.
The LTC4260 acknowledges this and then latches the lower
three bits of the command byte into its internal Register
Address pointer. The master then delivers the data byte
and the LTC4260 acknowledges once more and latches the
data into its internal register. The transmission is ended
when the master sends a STOP condition. If the master
continues sending a second data byte, as in a Write Word
command, the second data byte will be acknowledged
by
the LTC4260 but ignored (Figure 8).
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit set
to zero (Figure 9). The addressed LTC4260 acknowledges
this and then the master sends a command byte that in-
dicates which internal register the master wishes to read.
The LTC4260 acknowledges this and then latches the lower
three bits of the command byte into its internal Register
Address pointer. The master then sends a repeated START
condition followed by the same seven bit address with the

LTC4260CGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers 48V Hot Swap Controller with I2C ADC
Lifecycle:
New from this manufacturer.
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