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HSMP-389C-TR1G

P1-P3P4-P6P7-P9P10-P12P13-P13
7
Equivalent Circuit Model
HSMP-389x Chip*
Typical Applications for HSMP-489x Low Inductance Series
Microstrip Series Connection for HSMP-489x Series
In order to take full advantage of the low inductance
of the HSMP-489x series when using them in series ap-
plications, both lead 1 and lead 2 should be connected
together, as shown in Figure 17.
Co-Planar Waveguide Shunt Connection for HSMP-489x Series
Co-Planar waveguide, with ground on the top side of
the printed circuit board, is shown in Figure 20. Since
it eliminates the need for via holes to ground, it oers
lower shunt parasitic inductance and higher maximum
attenuation when compared to a microstrip circuit.
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, car-
rier lifetime.
1 2
3
Figure 16. Internal Connections.
HSMP-489x
Figure 17. Circuit Layout.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 18. Circuit Layout.
0.3 nH
0.3 nH
0.3 pF
1.5 nH 1.5 nH
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
0.12 pF*
* Measured at -20 V
0.5 Ω
R
j
R
s
C
j
R
j
=
20
Ω
I
0.9
R
T
= 0.5 + R
j
C
T
= C
P
+ C
j
I
= Forward Bias Current in mA
* See AN1124 for package models
Figure 21. Equivalent Circuit.
0.3 pF
0.75 nH
Figure 16. Internal Connections.
Figure 17. Circuit Layout.
Microstrip Shunt Connections for HSMP-489x Series
In Figure 18, the center conductor of the microstrip line
is interrupted and leads 1 and 2 of the HSMP-489x diode
are placed across the resulting gap. This forces the 1.5
nH lead inductance of leads 1 and 2 to appear as part of
a low pass lter, reducing the shunt parasitic inductance
and increasing the maximum available attenuation. The
0.3 nH of shunt inductance external to the diode is cre-
ated by the via holes, and is a good estimate for 0.032"
thick material.
Figure 18. Circuit Layout.
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Figure 21. Equivalent Circuit.
8
Assembly Information
0.026
0.075
0.016
0.035
Figure 22. PCB Pad Layout, SOT-363.
(dimensions in inches).
0.026
0.035
0.07
0.016
Figure 23. PCB Pad Layout, SOT-323.
(dimensions in inches).
0.037
0.95
0.037
0.95
0.079
2.0
0.031
0.8
DIMENSIONS IN
inches
mm
0.035
0.9
SOT-23 Footprint
Figure 24. PCB Pad Layout, SOT-23.
DIMENSIONS IN
inches
mm
0.075
1.9 0.071
1.8
0.112
2.85
0.079
2
0.033
0.85
0.041
1.05
0.108
2.75
0.033
0.85
0.047
1.2
0.031
0.8
0.033
0.85
Figure 25. PCB Pad Layout, SOT-143.
9
Lead-Free Reow Prole Recommendation (IPC/JEDEC J-STD-020C)
Reow Parameter Lead-Free Assembly
Average ramp-up rate (Liquidus Temperature (T
S(max)
to Peak) 3°C/ second max
Preheat Temperature Min (T
S(min)
) 150°C
Temperature Max (T
S(max)
) 200°C
Time (min to max) (t
S
) 60-180 seconds
Ts(max) to TL Ramp-up Rate 3°C/second max
Time maintained above: Temperature (T
L
) 217°C
Time (t
L
) 60-150 seconds
Peak Temperature (T
P
) 260 +0/-5°C
Time within 5 °C of actual Peak temperature (t
P
) 20-40 seconds
Ramp-down Rate 6°C/second max
Time 25 °C to Peak Temperature 8 minutes max
Note 1: All temperatures refer to topside of the package, measured on the package body surface
25
Time
Temperat ure
Tp
T
L
tp
t
L
t 25° C to Peak
Ra mp-up
ts
Ts
min
Ramp-down
Preh eat
Critical Zone
T
L
to Tp
Ts
max
Figure 26. Surface Mount Assembly Prole.
SMT Assembly
Reliable assembly of surface mount components is a
complex process that involves many material, process,
and equipment factors, including: method of heating
(e.g., IR or vapor phase reow, wave soldering, etc.) cir-
cuit board material, conductor thickness and pattern,
type of solder alloy, and the thermal conductivity and
thermal mass of components. Components with a low
mass, such as the SOT package, will reach solder reow
temperatures faster than those with a greater mass.
Avago Technologies’ diodes have been qualied to the
time-temperature prole shown in Figure 26. This prole
is representative of an IR reow type of surface mount
assembly process.
After ramping up from room temperature, the circuit
board with components attached to it (held in place
with solder paste) passes through one or more preheat
zones. The preheat zones increase the temperature of
the board and components to prevent thermal shock
and begin evaporating solvents from the solder paste.
The reow zone briey elevates the temperature su-
ciently to produce a reow of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to compo-
nents due to thermal shock. The maximum temperature
in the reow zone (T
MAX
) should not exceed 260°C.
These parameters are typical for a surface mount assem-
bly process for Avago Technologies diodes. As a general
guideline, the circuit board and components should be
exposed only to the minimum temperatures and times
necessary to achieve a uniform reow of solder.
P1-P3P4-P6P7-P9P10-P12P13-P13

HSMP-389C-TR1G

Mfr. #:
Buy HSMP-389C-TR1G
Manufacturer:
Broadcom / Avago
Description:
PIN Diodes 100 VBR 0.3 pF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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