NCP5210
http://onsemi.com
15
Application Circuit
Figure 18 shows the typical application circuit for
NCP5210. The NCP5210 is specifically designed as a total
power solution for the MCH and DDR memory system. This
diagram contains NCP5210 for driving four external N−Ch
FETs to form the DDR memory supply voltage (VDDQ) and
the MCH regulator.
Output Inductor Selection
The value of the output inductor is chosen by balancing
ripple current with transient response capability. A value of
1.7 H will yield about 3.0 A peak−to−peak ripple current
when converting from 5.0 V to 2.5 V at 250 kHz. It is
important that the rated inductor current is not exceeded
during full load, and that the saturation current is not less
than the expected peak current. Low ESR inductors may be
required to minimize DC losses and temperature rises.
Input Capacitor Selection
Input capacitors for PWM power supplies are required to
provide a stable, low impedance source node for the buck
regulator to convert from. The usual practice is to use a
combination of electrolytic capacitors and multi−layer
ceramic capacitors to provide bulk capacitance and high
frequency noise suppression. It is important that the
capacitors are rated to handle the AC ripple current at the
input of the buck regulators, as well as the input voltage. In
the NCP5210 the DDQ and MCH regulators are interleaved
(out of phase by 180°) to reduce the peak AC input current.
Output Capacitor Selection
Output capacitors are chosen by balancing the cost with
the requirements for low output ripple voltage and transient
voltage. Low ESR electrolytic capacitors can be effective at
reducing ripple voltage at 250 kHz. Low ESR ceramic
capacitors are most effective at reducing output voltage
excursions caused by fast load steps of system memory and
the memory controller.
Power MOSFET Selection
Power MOSFETs are chosen by balancing the cost with
the requirements for the current load of the memory system
and the efficiency of the converter provided. The selections
criteria can be based on the drain−to−source voltage,
drain−to−current, on−resistance R
DS(on)
, and input gate
capacitance. Low R
DS(on)
and high drain−to−current power
MOSFETs are usually preferred to achieve the high current
requirement of the DDR memory system and MCH, as well
as the high efficiency of the converter. The tradeoff is a
corresponding increase in the input gate capacitor of the
power MOSFETs.
PCB Layout Consideration
With careful PCB layout the NCP5210 can supply 20 A or
more current. It is very important to use wide traces or large
copper shades to carry current from the input node through
the MOSFET switches, inductor, and to the output filters and
load. Reducing the length of high current nodes will reduce
losses and reduce parasitic inductance. It is usually best to
locate the input capacitors, the MOSFET switches, and the
output inductor in close proximity to reduce DC losses,
parasitic inductance and radiated EMI.
The sensitive voltage feedback and compensation
networks should be placed near NCP5210 and away from
the switch nodes and other noisy circuit elements. Placing
compensation components near each other will minimize
the loop area and further reduce noise susceptibility.
Optional Boost Voltage Configuration
The charge pump circuit in Figure 19 can be used instead
of boost voltage scheme of Figure 18. The advantage in
Figure 19 is the elimination of the requirement for the Zener
clamp. The tradeoff is slightly less boost voltage and a
corresponding increase in MOSFET conduction losses.
Figure 19. Charge Pump Circuit at BOOT Pin
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
5VDUAL
COMP_1P5
TG_1P5
BG_1P5
GND_1P5
BUF_CUT
NCP5210
20
19
18
17
16
15
14
13
12
11
5VDUAL
TP2
R2
4.7
R3
1 k
R4
4.7
3
4
1
3
4
1
DPAK
Q2
NTD40N03
D1
BAT54HT1
L
D1
BAT54HT1
C4
5.6 nF
12VATX
TP2
2.5 VDDQ
TP5
C6
4.7
F
C7
2200
F
+ +
C25
2200
F
VDDQ
R15
1 k
D2
BAT54HT1
C27
100 nF
5VDUAL
Q2
NTD40N03
