LT3988
16
3988f
TIME
Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
3988 F07
Ratiometric Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
Figure 7. Two Different Modes of Output Voltage Tracking
applicaTions inForMaTion
Figure 8. Setup for Coincident and Ratiometric Tracking
Figure 9. Equivalent Input Circuit of Error Amplifier
At the input stage of the error amplifier, two common anode
diodes are used to clamp the equivalent reference voltage
and an additional diode is used to match the shifted com-
mon mode voltage. The top two current sources are of the
same amplitude. In the coincident mode, the TRACK/SS2
voltage is substantially higher than 0.75V at steady state
and effectively turns off D1. D2 and D3 will therefore con-
duct the same current and offer tight matching between
V
FB2
and the internal precision 0.75V reference. In the
ratiometric mode with R6 = R2, TRACK/SS2 equals 0.75V
at steady state. D1 will divert part of the bias current and
make V
FB2
slightly lower than 0.75V. Although this error
is minimized by the exponential I-V characteristic of the
diodes, it does impose a finite amount of output voltage
deviation. Further, when channel 1’s output experiences
dynamic excursions (under load transient, for example),
channel 2 will be affected as well. Setting R6 to a value
that pushes the TRK/SS2 voltage to 1V at steady state will
eliminate these problems while providing near ratiometric
tracking. The example shows channel 2 tracking channel 1,
however either channel may be set up to track the other.
Soft-Start
If a capacitor is tied from the TRACK/SS pin to ground,
then the internal pull-up current will generate a voltage
ramp on this pin. This results in a ramp at the output,
limiting the inductor current and therefore input current
during start-up. A good value for the soft-start capacitor
is C
OUT
/10,000, where C
OUT
is the value of the output
capacitor.
R5 R1
R6 R2
V
OUT2
R4
R3
TO
FB1
PIN
TO
TRK/SS2
PIN
TO
FB2
PIN
V
OUT1
COINCIDENT
R3
R4
R5 =
R6 =
RATIOMETRIC
R1
R1
V
OUT1
/1V – 1
SELECTING VALUES FOR R5 AND R6
3988 F08
1.36µA
+
I I
D1
TRACK/SS
0.75V
FB
D2
D3
3988 F09
g
m
R1
R2
=
V
OUT1
0.75
1,
R3
R4
=
V
OUT2
0.75
1
LT3988
17
3988f
applicaTions inForMaTion
Independent Input Voltages
V
IN1
and V
IN2
are independent and can be powered with
different voltages provided V
IN1
is present when V
IN2
is
present. Each supply must be bypassed as close to the V
IN
pins as possible. For applications requiring large inductors
due to high V
IN
to V
OUT
ratios, a 2-stage step-down ap-
proach may reduce inductor size by allowing an increase
in frequency. A dual step-down application steps down
the input voltage (V
IN1
) to the highest output voltage, then
uses that voltage to power the other output (V
IN2
). V
OUT1
must be able to provide enough current for its output plus
Figure 11. Subtracting the Current When the Switch Is ON (11a) From the Current When the Switch Is OFF (11b) Reveals the Path of
the High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and Boost Nodes Will Also Be Switched;
Keep These Nodes as Small as Possible. Finally, Make Sure the Circuit Is Shielded with a Local Ground Plane
the input current at V
IN2
when V
OUT2
is at maximum load.
Figure 10 shows a 12V to 5V, and 1.8V 2-stage converter
using this approach.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 11
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
Figure 10. 1MHz, 2-Stage Step-Down 5V and 1.8V Outputs
2200pF
57.6k 14k
6.8µH
V
IN
12V
V
OUT1
V
OUT1
5V, 500mA
V
OUT2
1.8V, 500mA
0.22µF
10µF
3988 F10
10.2k
2200pF
3.3µH
0.22µF
22µF
10k
FB1
DA1
SW1
BOOST1
SYNC
TRACK/SS1
FB2
DA2
SW2
BOOST2
BD
TRACK/SS2
EN/UVLO
GND
V
IN1
V
IN2
LT3988
40.2k
RT
4.7µF 4.7µF
V
IN
SW
GND
(11a)
V
IN
V
SW
C1 D1 C2
3988 F11
L1
SW
GND
(11c)
V
IN
SW
GND
(11b)
I
C1
LT3988
18
3988f
3988 F12
L2L1
D2
D1
C10C9
C2
C8C7
R7R6
R4 R3 R5
U1
C1
C3 C4
components should be as small as possible. Place these
components, along with the inductor and output capacitor,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of
the output capacitor. Additionally, keep the SW and BOOST
nodes as small as possible. Figure 12 shows an example
of proper PCB layout.
Thermal Considerations
The die temperature of the LT3988 must be lower than the
maximum rating of 125°C (150°C for the H-grade). This is
generally not a concern unless the ambient temperature is
above 85°C. For higher temperatures, care should be taken
in the layout of the circuit to ensure good heat sinking of
the LT3988. The maximum load current should be derated
as the ambient temperature approaches 125°C (150°C
applicaTions inForMaTion
Figure 12. Sample PC Board Layout
for the H-grade). The die temperature is calculated by
multiplying the LT3988 power dissipation by the thermal
resistance from junction to ambient. Power dissipation
within the LT3988 can be estimated by calculating the total
power loss from an efficiency measurement and subtract-
ing the catch diode loss. Thermal resistance depends on
the layout of the circuit board, but values from 30°C/W
to 60°C/W are typical.
Related Linear Technology Publications
Application Notes 19, 35, 44, 76 and 88 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1375
data sheet has a more extensive discussion of output
ripple, loop compensation, and stability testing. Design
Note 318 shows how to generate a dual polarity output
supply using a buck regulator.

LT3988HMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 60V Monolithic 1A Step-Down Switching Regulator
Lifecycle:
New from this manufacturer.
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