NCN8025 / NCN8025A
www.onsemi.com
9
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (V
DD
= 3.3 V; V
DDP
= 5 V; T
amb
= 25°C;
F
CLKIN
= 10 MHz)
Symbol UnitMaxTypMinParameter
|I
IH
|
|I
IL
|
PRES, PRES
High level input leakage current, V
IH
= V
DD
PRES
PRES
Low level input leakage current, V
IL
= 0 V
PRES
PRES
5
5
10
1
1
10
mA
T
debounce
Debounce time PRES and PRES (Note 9) 5 8 12 ms
I
CI/O
CI/O, CAUX1, CAUX2 current limitation − − 15 mA
I
CCLK
CCLK current limitation − − 70 mA
I
CRST
CRST current limitation − − 20 mA
T
act
Activation Time (Note 9) 30 − 100
ms
T
deact
Deactivation Time (Note 9) 30 − 250
ms
Temp
SD
Shutdown temperature (Note 9) − 150 − °C
9. Guaranteed by design and characterization.
POWER SUPPLY
The NCN8025 / NCN8025A smart card interface has two
power supplies: V
DD
and V
DDP
.
V
DD
is common to the system controller and the interface.
The applied V
DD
range can go from 2.7 V up to 5.5 V. If V
DD
goes below 2.30 V typical (UVLO
VDD
) a power−down
sequence is automatically performed. In that case the
interrupt (INT
) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 1.8 V, 3 V or 5 V power supply voltage
(CVCC) to the card. V
DDP
is the LDO’s input voltage.
CVCC is the LDO output. The typical distributed reservoir
output capacitor connected to CVCC is 100 nF + 220 nF. The
capacitor of 100 nF is connected as close as possible to the
CVCC’s pin and the 220 nF one as close as possible to the
card connector C1 pin. Both feature very low ESR values
(lower than 50 mW). The decoupling capacitors on V
DD
and
V
DDP
respectively 100 nF and 10 mF + 100 nF have also to
be connected close to the respective IC pins.
The CVCC pin can source up to 70 mA at 1.8 V, 3 V and
5 V continuously over the V
DDP
range (see corresponding
specification table), the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
The card V
CC
voltage (CVCC) can be programmed with
the pins VSEL0 and VSEL1 and according to the below table:
Table 1. CVCC PROGRAMMING
VSEL0 VSEL1 CVCC
0 0 3.0 V
0 1 5.0 V
1 0 3.0 V
1 1 1.8 V
VSEL0 can be used to select the CVCC programming
mode which can be 5V/3V
(VSEL0 connected to Ground)
or 1.8V/3V
(VSEL0 connected to V
DD
). VSEL0 and
VSEL1 are usually programmed before activating the smart
card interface that is when /CMDVCC is High.
There’s no specific sequence for applying V
DD
or V
DDP
.
They can be applied to the interface in any sequence. After
powering the device INT
pin remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the
Power−On Reset (POR) circuitry and the under−voltage
lockout (UVLO) detection (V
DD
voltage dropout
detection). PORADJ pin allows the user, according to the
considered application, to adjust the V
DD
UVLO threshold.
If not used PORADJ pin is connected to Ground
(recommended even if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no further
signal can be provided or supported during this period.
The system is ready to operate when the input voltage has
reached the minimum V
DD
. Considering this, the NCN8025
/ NCN8025A will detect an Under−Voltage situation when
the input supply voltage will drop below 2.30 V typical.
When V
DD
goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during power−on and power−off of
the V
DD
supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
UVLO +
R1 ) R2
R2
V
POR
(eq. 1)
If PORADJ is connected to Ground the V
DD
UVLO
threshold (V
DD
falling) is typically 2.30 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the V
DD
supply dropout detection
