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EL5130IS

P1-P3P4-P6P7-P9P10-P12
10
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FN7381.5
May 28, 2010
FIGURE 42. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 43. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
909mW
θ
J
A
=
1
1
0
°
C
/
W
S
O
8
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
435mW
θ
J
A
=
2
3
0
°
C
/
W
S
O
T
2
3
-
5
0 25 125 150
1.4
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
50
0.8
1.2
0.4
75 10085
0.6
1
0.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0 25 125 150
1
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
50
0.5
0.9
0.2
75 10085
0.3
0.7
0.1
0.4
0.8
0.6
625mW
391mW
θ
J
A
=2
5
6
°
C
/
W
S
O
T
2
3
-
5
θ
J
A
=
1
6
0
°
C
/
W
S
O
8
EL5130, EL5131
11
FN7381.5
May 28, 2010
EL5130, EL5131
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1
L
L1
DETAIL X
4° ±4°
SEATING
PLANE
e
H
b
C
0.010 BM CA
0.004 C
0.010 BM CA
B
D
(N/2)
1
E1
E
NN
(N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
12
FN7381.5
May 28, 2010
EL5130, EL5131
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
1.60
2.80
0.05-0.15
1.14 ±0.15
0.20 C A-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
0.08-0.20
SEE DETAIL X
1.45 MAX
(0.60)
0-3°
C
B
A
D
3
3
3
0.20 C
(1.90)
2x
0.15 C
2x
D
0.15 C
2x
A-B
(0.25)
H
5
2
4
5
5
END VIEW
PLANE
P1-P3P4-P6P7-P9P10-P12

EL5130IS

Mfr. #:
Buy EL5130IS
Manufacturer:
Renesas / Intersil
Description:
IC OPAMP VFB 1 CIRCUIT 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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