LTC4313-1/LTC4313-2/
LTC4313-3
16
4313123f
applicaTions inForMaTion
Figure 9. The LTC4313-1 Operating in a Cascade with Other LTC Buffers
with Active RTAs. Only the Clock Pathway is Shown for Simplicity
LTC4313-1
GND
V
CC
SCLOUTSCLIN
SCL1
SCL2
R1
5k
C1
0.01µF
3.3V
LTC4300A
GND
V
CC
SCLOUT
SCL3
SCLIN
R3
2.7k
5V
R2
2.7k
4313123 F09
C
B1
100pF
* C
B2
690pF
LTC4307
GND
V
CC
SCLOUT
SCL4
I/O CARD #5
I/O CARD #2-4
SCLIN
R4
5k
BACKPLANE
I/O CARD #1
* PARASITIC BACKPLANE CAPACITANCE
Figure 10. Corresponding SCL Switching Waveforms.
No Glitches Are Seen
2V/DIV
2V/DIV
2V/DIV
1µs/DIV
4313123 F10
LTC4300A/
LTC4307
RTAs
TURN ON
LTC4313
BUFFERS
TURN OFF
LTC4313-1
RTA ON
SCL2
SCL3
SCL1
LTC4313-1/LTC4313-2/
LTC4313-3
17
4313123f
applicaTions inForMaTion
Figure 11. Recommended Maximum R1 and C
B1
Values for the
LTC4313 Operating with Multiple LTC4300As in a 3.3V System
Figure 12. Recommended Maximum R1 and C
B1
Values for the
LTC4313 Operating with Multiple LTC4307s in a 3.3V System
Figure 14. LTC4313-1s in a Repeater Application
R
BUS
(kΩ)
0
C
BUS
(pF)
100
1000
8
4313123 F11
10
2
64
10
M = 1
M = 2
M = 3
R
BUS
(kΩ)
0
C
BUS
(pF)
1000
10000
8
4313123 F12
100
2
64
10
M = 1
LTC4313-1
GND
V
CC
4313123 F14
READY
SCLOUT
SDAOUT
ENABLE
SCLIN
SDAIN
SCL1
SDA1
R2
10k
R3
10k
R4
10k
R1
10k
C1
0.01µF
3.3V
LTC4313-3
GND
V
CC
READY
SCLOUT
SDAOUT
ENABLE
SCLIN
SDAIN
LTC4313-1
GND
V
CC
READY
SCLOUT
SDAOUT
ENABLE
SCLIN
SDAIN
R6
10k
R5
10k
R9
10k
R8
10k
R7
10k
SCL2
SDA2
Figure 13. Communication with a Non-Compliant
I
2
C Device Using the LTC4313
LTC4313
GND
V
CC
4313123 F13
SCLOUT
SDAOUT
DISCEN
ENABLE
READY
SCLIN
SDAIN
R5
10k
R3
10k
R2
10k
R1
10k
R4
10k
C1
0.01µF
NON-COMPLIANT
I
2
C DEVICE
V
OL
= 0.6V
5V
3.3V
µP
LTC4313-1/LTC4313-2/
LTC4313-3
18
4313123f
package DescripTion
DD8 Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ± 0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC4313IDD-3#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - Signal Buffers, Repeaters 2-Wire Bus Bufs w/ Hi N Margin
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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