LTC4313IDD-3#PBF Datasheet LTC4313IMS8-3#TRPBF, LTC4313IDD-3#TRPBF, LTC4313IMS8-3#PBF | P7-P9

LTC4313-1/LTC4313-2/

LTC4313-3

4313123f

operaTion

The LTC4313 is a high noise margin bus buffer which

provides capacitance buffering for I

C signals. Capacitance

buffering is achieved by using back to back buffers on

the clock and data channels which isolate the SDAIN

and SCLIN capacitances from the SDAOUT and SCLOUT

capacitances respectively. All SDA and SCL pins are fully

bidirectional. The high noise margin allows the LTC4313 to

operate with non-compliant I

C devices that drive a high

, permits a number of LTC4313s to be connected in

series and improves the reliability of I

C communications

in large noisy systems. Rise time accelerator (RTA) pull-up

currents (I

RTA

) turn on during rising edges to reduce bus

rise time for the LTC4313-1 and LTC4313-2. In a typical

application the input and output busses are pulled up to

although this is not a requirement. If V

DD,BUS

is not

tied to V

, V

DD,BUS

must be greater than V

to prevent

overdrive of the bus by the RTAs for the LTC4313-1 and

LTC4313-2. See the Applications Information section for

DD,BUS

requirements for the LTC4313-3.

When the LTC4313 first receives power on its V

pin, it

starts out in an undervoltage lockout mode (UVLO) until

its V

exceeds 2.7V. The buffers and RTAs are disabled

and the LTC4313 ignores the logic state of its clock and

data pins. During this time the precharge circuit forces a

nominal voltage of 1V on the SDA and SCL pins through

200k resistors.

Once the LTC4313 exits UVLO and its ENABLE pin has

been asserted high, it monitors the clock and data pins

for a stop bit or a bus idle condition. When a combination

of either condition is detected simultaneously on the input

and output sides, the LTC4313 activates the connection

between SDAIN and SDAOUT, and SCLIN and SCLOUT,

respectively, asserts READY high and deactivates the

precharge circuit. RTAs for the LTC4313-1 and LTC4313-2

are also enabled at this time.

When a SDA/SCL pin is driven below the V

level, the

buffers are turned on and the logic low level is propagated

though the LTC4313 to the other side. A high occurs when

all devices on the input and output sides release high. Once

the bus voltages rise above the V

level, the buffers are

turned off. The RTAs are turned on at a slightly higher volt-

age. The RTAs accelerate the rising edges of the SDA/SCL

inputs and outputs up to a voltage of 0.9•V

, provided

that the busses on their own are rising at a minimum rate

of 0.4V/µs as determined by the slew rate detectors. The

RTAs are configured to operate in a strong slew limited

switch mode in the LTC4313-1 and in the current source

mode in the LTC4313-2.

The LTC4313 detects a bus stuck low (fault) condition

when both clock and data busses are not simultaneously

high at least once in 45ms. When a stuck bus occurs, the

LTC4313 disconnects the input and output sides and after

waiting at least 40µs, generates up to sixteen 5.5kHz clock

pulses on the SCLOUT pin and a stop bit to attempt to free

the stuck bus. Should the stuck bus release high during

this period, automatic clock generation is terminated.

Once the stuck bus recovers, connection is re-established

between the input and output after a stop bit or bus idle

condition is detected. Toggling ENABLE after a fault condi-

tion has occurred forces a connection between the input

and output. When powering into a stuck low condition, the

input and output sides remain disconnected even after the

LTC4313 has exited the UVLO mode as a stop bit or bus

idle condition is not detected on the stuck busses. After

the timeout period, a stuck low fault condition is detected

and the behavior is as described previously.

LTC4313-1/LTC4313-2/

LTC4313-3

4313123f

The LTC4313 provides capacitance buffering, data and

clock Hot Swap capability and level translation. The high

noise margin of the LTC4313 permits interoperability with

C devices that drive a high V

permits series connec-

tion of multiple LTC4313s and improves I

C communica-

tion reliability. The LTC4313 isolates backplane and card

capacitances and provides slew control of falling edges

while level translating 3.3V and 5V busses. The LTC4313-1

and LTC4313-2 also provide pull-up currents to accelerate

rising edges. These features are illustrated in the following

subsections.

Rise Time Accelerator (RTA) Pull-Up Current Strength

(LTC4313-1 and LTC4313-2)

After an input and output connection has been established,

the RTAs on both the input and output sides of the SDA

and SCL busses are activated. During positive bus transi-

tions of at least 0.4V/µs, the RTAs provide pull-up cur-

rents to reduce rise time. The RTAs allow users to choose

larger bus pull-up resistors to reduce power consumption

and improve logic low noise margins, design with bus

capacitances outside of the I

C specification or to oper-

ate at a higher clock frequency. The LTC4313-1 regulates

its RTA current to limit the bus rise rate to a maximum

applicaTions inForMaTion

Figure 1. Bus Rising Edge for the LTC4313-1. V

= V

DD,BUS

= 5V Figure 2. Bus Rising Edge for the LTC4313-2. V

= V

DD,BUS

= 5V

of 75V/µs. The current is therefore directly proportional

to the bus capacitance. The LTC4313-1 RTA is capable of

sourcing up to 40mA of current. Rise time acceleration

for the LTC4313-2 is provided by a 2.5mA current source.

Figures 1 and 2 show the rising waveforms of heavily

loaded SDAIN and SDAOUT busses for the LTC4313-1 and

LTC4313-2 respectively. In both figures, during a rising

edge, the buffers are active and the input and output sides

are connected, until the bus voltages on both the input

and output sides are greater than 0.3 • V

. When each

individual bus voltage rises above 0.41 • V

, the RTA on

that bus turns on. The effect of the acceleration strength

is shown in the waveforms in Figures 1 and 2 for identi-

cal bus loads. The RTAs of the LTC4313-1 and LTC4313-2

supply 10mA and 2.5mA of pull-up current respectively for

the bus conditions shown in Figures 1 and 2. For identical

bus loads, the bus rises faster in Figure 1 compared to

Figure 2 because of the higher I

RTA

The RTAs are internally disabled during power-up and dur-

ing a bus stuck low event. The RTAs when activated pull

the bus up to 0.9•V

on the input and output sides of the

SDA and SCL pins. In order to prevent bus overdrive by

the RTA, the bus supplies on the input and output sides

2V/DIV

1µs/DIV

4313123 F01

= V

DD,BUS

= 5V

BUS

= 20k

= C

OUT

= 200pF

SDAIN

SDAOUT

2V/DIV

1µs/DIV

4313123 F02

= V

DD,BUS

= 5V

BUS

= 20k

= C

OUT

= 200pF

SDAIN

SDAOUT

LTC4313-1/LTC4313-2/

LTC4313-3

4313123f

of the LTC4313-1 and LTC4313-2 must be greater than

or equal to 0.9•V

. An example is shown in Figure 3

where the input bus voltage is greater than V

. During a

rising edge, the input bus rise rate will be accelerated by

the RTA up to a voltage of 2.97V after which the bus rise

rate will reduce to a value that is determined by the bus

current and bus capacitance. The RTA turn-off voltage is

less than the bus supply and the bus is not overdriven.

Pull-Up Resistor Value Selection

To guarantee that the RTAs are activated during a rising

edge, the bus must rise on its own with a positive slew rate

of at least 0.4V/µs. To achieve this, choose a maximum

BUS

using the formula:

BUS

≤

DD,BUS(MIN)

− V

RTA(TH)

( )

0.4

µs

• C

BUS

(1)

BUS

is the pull-up resistor, V

DD,BUS(MIN)

is the minimum

bus pull-up supply voltage, V

RTA(TH)

is the voltage at which

the RTA turns on and C

BUS

is the equivalent bus capaci-

tance. R

BUS

must also be large enough to guarantee that:

BUS

≥

DD,BUS(MAX)

− 0.4V

( )

4mA

(2)

This criterion ensures that the maximum bus current is

less than 4mA.

applicaTions inForMaTion

Input to Output Offset Voltage

While propagating a logic low voltage on its SDA and SCL

pins, the LTC4313 introduces a positive offset voltage

between the input and output. When a logic low voltage

≥200mV is driven on any of the LTC4313’s clock or data

pins, the LTC4313 regulates the voltage on the opposite

side to a slightly higher value. This is illustrated in Equa-

tion 3, which uses SDA as an example:

SDAOUT

= V

SDAIN

+ 50mV + 15Ω •

DD,BUS

BUS

(3)

In Equation 3, V

DD,BUS

is the output bus supply voltage

and R

BUS

is the SDAOUT bus pull-up resistance.

For driven logic low voltages < 200mV Equation 3 does

not apply as the saturation voltage of the open collector

output transistor results in a higher offset. For a driven input

logic low voltage below 220mV, the output is guaranteed

to be below a V

of 400mV for bus pull-up currents up to

4mA. See the Typical Performance Characteristics section

for offset variation as a function of the driven logic low

voltage and bus pull-up current.

Figure 3. Level Shift Application Where the SDAIN and SCLIN Bus Pull-Up

Supply Voltage Is Higher Than the Supply Voltage of the LTC4313

LTC4313-1

GND

4313123 F03

READY

SCLOUT

SDAOUT

ENABLE

SCLIN

SDAIN

SCL1

SDA1

10k

0.01µF

10k

READY

SCL2

SDA2

10k

3.3V

10k

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC4313IDD-3#PBF

Mfr. #:

Buy LTC4313IDD-3#PBF

Manufacturer:

Analog Devices Inc.

Description:

Interface - Signal Buffers, Repeaters 2-Wire Bus Bufs w/ Hi N Margin

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LTC4313IDD-3#PBF

LTC4313IDD-3#PBF

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