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9FG108EFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 4
ICS9FG108E REV C 102912
Pin Descriptions (cont.)
PIN # PIN NAME PIN TYPE DESCRIPTION
25 DIF_STOP# IN Active low input to stop differential output clocks.
26 vSPREAD IN
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
27 ^SEL14M_25M# IN
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
28 vOE_3 IN
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
29 DIF_3# OUT 0.7V differential Complementary clock output
30 DIF_3 OUT 0.7V differential true clock output
31 VDD PWR Power supply, nominal 3.3V
32 DIF_2# OUT 0.7V differential Complementary clock output
33 DIF_2 OUT 0.7V differential true clock output
34 ^OE_2 IN
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
35 GND PWR Ground pin.
36 VDD PWR Power supply, nominal 3.3V
37 ^OE_1 IN
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
38 DIF_1# OUT 0.7V differential Complementary clock output
39 DIF_1 OUT 0.7V differential true clock output
40 VDD PWR Power supply, nominal 3.3V
41 DIF_0# OUT 0.7V differential Complementary clock output
42 DIF_0 OUT 0.7V differential true clock output
43 vOE_0 IN
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
44 vFS1 IN 3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
45 vFS0 IN 3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
46 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
47 GNDA PWR Ground pin for the PLL core.
48 VDDA PWR 3.3V power for the PLL core.
Note:
^ indicates internal 120K pull up
v indicates internal 120K pull down
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 5
ICS9FG108E REV C 102912
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS9FG108E. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–REF-14.318/25 MHz
Electrical Characteristics–Differential Phase Jitter Parameters
C
T
A
= T
AMBIENT
; V
DD
= 3.3 V +/-5%;R
S
=33
Ω,
C
L
= 5 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.4 V 1
Rise t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V 1 1.4 2.5 ns 1
Fall Time t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V 1 1.4 2.5 ns 1
Duty Cycle d
t1
V
T
= 1.5 V 455355%1
Jitter t
jcyc-cycCOM
VT = 1.5 V (commercial) 87 200 ps 1
Jitter t
jcyc-cycIND
VT = 1.5 V (industrial) 87 250 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Trim capacitors must be used to tune the REF to the exact Crystal Frequency.
T
A
= Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%
PARAMETER Symbol Conditions Min Typ Max Units Notes
t
jp
hasePLL
PCIe Gen 1 25.2 86 ps (p-p) 1,2
t
jphaseLo
PCIe Gen1/2
10kHz < f < 1.5MHz
0.8 3
ps
(RMS)
1,2
t
jphaseHigh
PCIe Gen1/2
1.5MHz < f < Nyquist (50MHz)
1.8
3.1
ps
(RMS)
1,2
t
jphQPI
QPI 133MHz 4.8G/6.4Gb,12UI 0.2 0.5
ps
(RMS)
1,3
t
jphFBD3.2G
FBD specs
(11 to 33MHz)
1.4 3
ps
(RMS)
1
t
jphFBD4.8G
FBD specs
1.1 2.5
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
See http://www.pcisig.com for complete specs
3
First number is 4.8G link speed, second number is 6.4G link speed. From Intel Clock Jit tool
Jitter, Phase
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 6
ICS9FG108E REV C 102912
Electrical Characteristics–Input/Supply/Common Output Parameters
T
A
= T
AMBIENT
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Tambient T
COM
Commericial Temperature 0 70 °C
Tambient T
IND
Industrial Temperature -40 85 °C
Input High Voltage V
IH
3.3 V +/-5% 2
V
DD
+ 0.3
V1
Input Low Voltage V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
IDD
VDD
182 205 mA 1
IDD
VDDA
20 25 mA 1
IDD
VDD
153 175 mA 1
IDD
VDDA
19 25 mA 1
IDD
VDDPD
146 165 mA 1
IDD
VDDAP
D
19 25 mA 1
IDD
VDDPD
26 35 mA 1
IDD
VDDAPD
19 25 mA 1
IDD
VDD
181 225 mA 1
IDD
VDDA
21 28 mA 1
IDD
VDD
152 180 mA 1
IDD
VDDA
20 28 mA 1
IDD
VDDPD
145 175 mA 1
IDD
VDDAP
D
20 28 mA 1
IDD
VDDPD
26 38 mA 1
IDD
VDDAPD
20 28 mA 1
SEL14M_25M# = 0 22.50 25 28.00 MHz 3
SEL14M_25M# = 1 12.89 14.318 15.75 MHz 3
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
T
STABcom
From V
DD
Power-Up to 1st
clock
1.2 1.8 ms 1,2
T
STABind
From V
DD
Power-Up to 1st
clock
1.8 3 ms 1,2
SEL14M_25M# = 0 30 31.5 33 kHz 1,3,4
SEL14M_25M# = 1 30 31.5 33 kHz 1,3,4
Spread Modulation % f
MOD%DWN
Down Spread Selected -0.5 % 1,3,4
Spread Modulation % f
MOD%CT
R
Center Spread Selected +/-0.25 % 1,3,4
DIF output enable
t
DIFOE
DIF output enable after 15 ns 1
Input Rise and Fall times
t
R
/t
F
20% to 80% of VDD 5 ns 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
See timin
g
dia
g
rams for timin
g
requirements.
Input Low Current
Operating Supply Current
(T
A
= Commercial)
C
L
=Full load; fout = 400 MHz
C
L
=Full load; fout = 100 MHz
C
L
=Full load; fout = 100 MHz
DIF_STOP# Current
(T
A
= Industrial)
All DIF pairs stopped in driven
mode
All DIF pairs stopped in Hi-Z
mode
f
MOD
DIF_STOP# Current
(T
A
= Commercial)
All DIF pairs stopped in driven
mode
All DIF pairs stopped in Hi-Z
mode
Operating Supply Current
(T
A
= Industrial)
C
L
=Full load; fout = 400 MHz
3
Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
ppm frequenc
y
accurac
y
on PLL outputs.
4
These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale
these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz
input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz.
Input Frequency
3
F
i
Input/Output
Capacitance
1
Clk Stabilization
1,2
Spread Modulation
Frequenc
y
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9FG108EFLF

Mfr. #:
Buy 9FG108EFLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 8 O/P PCIE G2 SYNTH
Lifecycle:
New from this manufacturer.
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