9FG108EFLF Datasheet 9FG108EGILFT, 9FG108EFLFT, 9FG108EGLFT | P7-P9

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 7

ICS9FG108E REV C 102912

Electrical Characteristics–DIF 0.7V Current Mode Differential Pair

= T

AMBIENT

; V

= 3.3 V +/-5%; C

=2pF, R

=33.2

Ω

, R

=49.9

Ω

, I

REF

= 475

Ω

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Current Source Output

Impedance

= V

3000

Ω

Voltage High VHigh 660 750 850 1

Volta

e Lo

VLow -150 3 150 1

Max Voltage Vovs 1150 1

Min Voltage Vuds -300 1

Crossin

Volta

e (abs) Vcross(abs) 250 336 550 mV 1

Crossing Voltage (var) d-Vcross Crossing variation over all edges 40 140 mV 1

14.3M input, SS OFF -300 300 ppm 1,2,5

14.3M input, SS ON -300 300 ppm 1,2,5

25M input SS OFF -50 50 ppm 1,2,5

25M input, SS ON -300 300 ppm 1,2,5

400MHz nominal 2.4993 2.5008 ns 2

400MHz spread 2.4993 2.5133 ns 2,3

333.33MHz nominal 2.9991 3.0009 ns 2

333.33MHz spread 2.9991 3.016 ns 2,3

266.66MHz nominal 3.7489 3.7511 ns 2

266.66MHz spread 3.7489 3.77 ns 2,3

200MHz nominal 4.9985 5.0015 ns 2

200MHz spread 4.9985 5.0266 ns 2,3

166.66MHz nominal 5.9982 6.0018 ns 2

166.66MHz spread 5.9982 6.0320 ns 2,3

133.33MHz nominal 7.4978 7.5023 ns 2

133.33MHz spread 7.4978 5.4000 ns 2,3

100.00MHz nominal 9.9970 10.0030 ns 2

100.00MHz spread 9.9970 10.0533 ns 2,3

400MHz nominal/spread 2.4143 ns 1,2

333.33MHz nominal/spread 2.9141 ns 1,2

266.66MHz nominal/spread 3.6639 ns 1,2

200MHz nominal/spread 4.8735 ns 1,2

166.66MHz nominal/spread 5.8732 ns 1,2

133.33MHz nominal/spread 7.3728 ns 1,2

100.00MHz nominal/spread 9.8720 ns 1,2

Rise Time t

= 0.175V, V

= 0.525V 175 241 700 ps 1

Fall Time t

= 0.525V V

= 0.175V 175 260 700 ps 1

Rise Time Variation d-t

018125 ps 1

Fall Time Variation d-t

019125 ps 1

Duty Cycle d

Measured Differentially 45 50 55 % 1

sk3COM

= Commercial, V

=50% 30 50 ps 1

sk3IND

= Industrial, V

=50% 35 65 ps 1

Jitter, Cycle to cycle t

jcyc-cyc

Measurement from differential

wavefrom

17 50 ps 1

Guaranteed by design and characterization, not 100% tested in production.

All Long Term Accuracy

Figures are for down spread.

+/- 50 ppm at any frequency with spread off

Skew, output to output

This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit

http://www.pcisig.com for additional details

Long Accuracy ppm

Average period Tperiod

Absolute min period T

absmin

Statistical measurement on

single ended signal using

oscilloscope math function.

Measurement on single ended

signal using absolute value.

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 8

ICS9FG108E REV C 102912

General SMBus Serial Interface Information for ICS9FG108E

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

O O

Byte N + X - 1

ACK

PstoP bit

Read Address Write Address

(H)

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

O O

Byte N + X - 1

N Not acknowledge

PstoP bit

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 9

ICS9FG108E REV C 102912

SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)

Pin # Name Control Function T

e0 1Defaul

Bit 7

RW Pin 27

Bit 6

RW Pin 5

Bit 5

RW Pin 44

Bit 4

RW Pin 7

Bit 3

RW Off On Pin 26

Bit 2

Hardware

Select

Software

Select

Bit 1

RW Driven Hi-Z 0

Bit 0

RW Down Center 0

Notes:

1. These bits reflect the state of the corresponding pins at power up, but may be written to

if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.

SMBus Table: Output Enable Register

Pin # Name Control Function T

e0 1Defaul

Bit 7

DIF_7 EN Output Enable RW Disable Enable 1

Bit 6

DIF_6 EN Output Enable RW Disable Enable 1

Bit 5

DIF_5 EN Output Enable RW Disable Enable 1

Bit 4

DIF_4 EN Output Enable RW Disable Enable 1

Bit 3

DIF_3 EN Output Enable RW Disable Enable 1

Bit 2

DIF_2 EN Output Enable RW Disable Enable 1

Bit 1

DIF_1 EN Output Enable RW Disable Enable 1

Bit 0

DIF_0 EN Output Enable RW Disable Enable 1

Note:

SMBus Table: Output Stop Mode Register

Pin # Name Control Function T

e0 1Defaul

Bit 7

DIF_7 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 6

DIF_6 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 5

DIF_5 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 4

DIF_4 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 3

DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 2

DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 1

DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

Bit 0

DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0

See Frequency

Selection Table,

Page 1

FS3

FS2

FS1

FS0

te 2

Byte 1 sets outputs active or inactive, not the conditons set by the OE inputs.

te 1

Spread Enable

Enable Software Control of Frequency,

Spread Enable (Spread Type always

Software Control)

- DIF_STOP# drive mode

- Spread Type

te 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

9FG108EFLF

Mfr. #:

Buy 9FG108EFLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner 8 O/P PCIE G2 SYNTH

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

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9FG108EFLF

9FG108EFLF

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