1 XIN/CLKIN IN Crystal input or Reference Clock input
2 X2 OUT Crystal output, Nominally 14.318MHz
3 VDD PWR Power supply, nominal 3.3V
4 GND PWR Ground pin.
5 REFOUT OUT Reference Clock output
6 vFS2 IN Frequency select pin. This pin has an internal 120k pull down resistor
7vOE_7 IN
Active high input for enabling output 7. This pin has a 120kohm pull down.
0 = tri-state outputs, 1= enable outputs
8 DIF_7 OUT 0.7V differential true clock output
9 DIF_7# OUT 0.7V differential Complementary clock output
10 VDD PWR Power supply, nominal 3.3V
11 DIF_6 OUT 0.7V differential true clock output
12 DIF_6# OUT 0.7V differential Complementary clock output
13 ^OE_6 IN
Active high input for enabling output 6. This pin has an internal 120kohm pull up.
0 = tri-state outputs, 1= enable outputs
14 VDD PWR Power supply, nominal 3.3V
15 GND PWR Ground pin.
16 ^OE_5 IN
Active high input for enabling output 5. This pin has an internal 120kohm pull up.
0 = tri-state outputs, 1= enable outputs
17 DIF_5 OUT 0.7V differential true clock output
18 DIF_5# OUT 0.7V differential Complementary clock output
19 VDD PWR Power supply, nominal 3.3V
20 DIF_4 OUT 0.7V differential true clock output
21 DIF_4# OUT 0.7V differential Complementary clock output
22 vOE_4 IN
Active high input for enabling output 4. This pin as an internal 120kohm pull down.
0 = tri-state outputs, 1= enable outputs
23 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
24 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
Note:
^ indicates internal 120K pull up
