9FG108EGLFT Datasheet 9FG108EGILFT, 9FG108EFLFT, 9FG108EGLFT | P10-P12

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 10

ICS9FG108E REV C 102912

SMBus Table: Frequency Select Readback Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

SEL14M_25M#

1

(FS3)

State of pin 27 R Pin 27

Bit 6

FS2

1

State of pin 6 R Pin 6

Bit 5

FS1

1

State of pin 44 R Pin 44

Bit 4

FS0

1

State of pin 45 R Pin 45

Bit 3

SPREAD

1

State of pin 26 R Off On Pin 26

Bit 2

RX

Bit 1

RX

Bit 0

RX

Notes:

1. These bits reflect the state of the corresponding pins, regardless of whether software

programming is enabled or not.

SMBus Table: Vendor & Revision ID Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

RID3 R X

Bit 6

RID2 R X

Bit 5

RID1 R X

Bit 4

RID0 R X

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

SMBus Table: DEVICE ID

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

DEVID7 R 0

Bit 6

DEVID6 R 0

Bit 5

DEVID5 R 0

Bit 4

DEVID4 R 0

Bit 3

DEVID3 R 1

Bit 2

DEVID2 R 0

Bit 1

DEVID1 R 0

Bit 0

DEVID0 R 0

SMBus Table: Byte Count Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 0

Bit 2

BC2 RW - - 1

Bit 1

BC1 RW - - 1

Bit 0

BC0 RW - - 1

-

B

y

te 5

-

B

y

te 6

Writing to this register

will configure how many

bytes will be read back,

default is 07

= 7 bytes.

-

VENDOR ID

-

Reserved Reserved

B

y

te 4

-

REVISION ID

-

Rev E = 1000

26

Reserved Reserved

45

44

See Frequency

Selection Table,

Page 1

B

y

te 3

6

27

Device ID = 08 hex

Reserved

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 11

ICS9FG108E REV C 102912

SMBus Table: Reserved Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

SMBus Table: Reserved Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

SMBus Table: M/N Programming Enable

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

M/N_EN

PLL M/N Programming

Enable

RW Disable Enable 0

Bit 6

OE_Polarity

Select Polarity of OE

inputs

RW OE# OE

1

Bit 5

REFOUT_En

Enables/Disables REF RW Disable Enable

1

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

SMBus Table: PLL Frequency Control Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

PLL N Div8 N Divider Prog bit 8 RW X

Bit 6

PLL N Div9 N Divider Prog bit 9 RW X

Bit 5

PLL M Div5 RW X

Bit 4

PLL M Div4 RW X

Bit 3

PLL M Div3 RW X

Bit 2

PLL M Div2 RW X

Bit 1

PLL M Div1 RW X

Bit 0

PLL M Div0 RW X

Reserved

B

y

te 8

Reserved

B

y

te 7

Reserved

5

Reserved

B

y

te 9

-

Reserved

B

y

te 10

-

The decimal

representation of M and

N Divider in Byte 11 and

12 will configure the PLL

VCO frequency.

Default at power up =

latch-in or Byte 0 Rom

table. VCO Frequency

= fXTAL x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

-

M Divider Programming

bit (5:0)

-

ICS9FG108E

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA

IDT®

FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 12

ICS9FG108E REV C 102912

SMBus Table: PLL Frequency Control Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

PLL N Div7 RW X

Bit 6

PLL N Div6 RW X

Bit 5

PLL N Div5 RW X

Bit 4

PLL N Div4 RW X

Bit 3

PLL N Div3 RW X

Bit 2

PLL N Div2 RW X

Bit 1

PLL N Div1 RW X

Bit 0

PLL N Div0 RW X

SMBus Table: PLL Spread Spectrum Control Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

PLL SSP7 RW X

Bit 6

PLL SSP6 RW X

Bit 5

PLL SSP5 RW X

Bit 4

PLL SSP4 RW X

Bit 3

PLL SSP3 RW X

Bit 2

PLL SSP2 RW X

Bit 1

PLL SSP1 RW X

Bit 0

PLL SSP0 RW X

SMBus Table: PLL Spread Spectrum Control Register

Pin # Name Control Function T

yp

e0 1Defaul

t

Bit 7

0

Bit 6

PLL SSP14 RW X

Bit 5

PLL SSP13 RW X

Bit 4

PLL SSP12 RW X

Bit 3

PLL SSP11 RW X

Bit 2

PLL SSP10 RW X

Bit 1

PLL SSP9 RW X

Bit 0

PLL SSP8 RW X

-

- Reserved

-

Spread Spectrum

Programming bit(14:8)

These Spread

Spectrum bits in

Byte 13 and 14 will

program the spread

pecentage of PLL

-

These Spread

Spectrum bits in

Byte 13 and 14 will

program the spread

pecentage of PLL

-

B

y

te 13

B

y

te 12

-

N Divider Programming

Byte11 bit(7:0) and

Byte10 bit(7:6)

-

Spread Spectrum

Programming bit(7:0)

The decimal

representation of M and

N Divider in Byte 11 and

12 will configure the PLL

VCO frequency.

Default at power up =

latch-in or Byte 0 Rom

table. VCO Frequency

= fXTAL x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

-

B

y

te 11

-

9FG108EGLFT

9FG108EGLFT

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