AT25128AW-10SU-1.8 Datasheet AT25128A-10PU-2.7, AT25128A-10TU-2.7, AT25128AN-10SU-1.8 | P10-P12

3368J–SEEPR–06/07

AT25128A_256A

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of

four levels of protection. The AT25128A/256A is divided into four array segments. Top quarter

(1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any

selected segment will therefore be read only. The block write protection levels and correspond-

ing status register control bits are shown in Table 3-4.

The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and

functions as the regular memory cells (e.g. WREN, t

, RDSR).

The WRSR instruction also allows the user to enable or disable the write protect (WP) pin

through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled

when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when

either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,

writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-

protected sections in the memory array are disabled. Writes are only allowed to sections of the

memory which are not block-protected.

NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as

long as the WP pin is held low.

READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the follow-

ing sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted

via the SI line followed by the byte address to be read (see Table 3-6 on page 11). Upon com-

pletion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is

then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high

after the data comes out. The read sequence can be continued since the byte address is auto-

matically incremented and data will continue to be shifted out. When the highest address is

Table 3-4. Block Write Protect Bits

Level

Status Register Bits Array Addresses Protected

BP1 BP0 AT25128A AT25256A

0 0 0 None None

1(1/4) 0 1 3000 – 3FFF 6000 – 7FFF

2(1/2) 1 0 2000 – 3FFF 4000 – 7FFF

3(All) 1 1 0000 – 3FFF 0000 – 7FFF

Table 3-5. WPEN Operation

WPEN WP WEN

Protected

Blocks

Unprotected

Blocks

Status

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

3368J–SEEPR–06/07

AT25128A_256A

reached, the address counter will roll over to the lowest address allowing the entire memory to

be read in one continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate instruc-

tions must be executed. First, the device must be write enabled via the Write Enable (WREN)

Instruction. Then a Write instruction may be executed. Also, the address of the memory loca-

tion(s) to be programmed must be outside the protected address field location selected by the

Block Write Protection Level. During an internal write cycle, all commands will be ignored except

the RDSR instruction.

A Write Instruction requires the following sequence. After the CS line is pulled low to select the

device, the Write op-code is transmitted via the SI line followed by the byte address and the data

(D7 - D0) to be programmed (see Table 3-6). Programming will start after the

CS pin is brought

high. (The Low-to-High transition of the

CS pin must occur during the SCK low time immediately

after clocking in the D0 (LSB) data bit.

The Ready/Busy status of the device can be determined by initiating a Read Status Register

(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has

ended. Only the Read Status Register instruction is enabled during the Write programming

cycle.

The AT25128A/256A is capable of a 64-byte Page Write operation. After each byte of data is

received, the six low order address bits are internally incremented by one; the high order bits of

the address will remain constant. If more than 64 bytes of data are transmitted, the address

counter will roll over and the previously written data will be overwritten. The AT25128A/256A is

automatically returned to the write disable state at the completion of a Write cycle.

NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction

and will return to the standby state, when CS is brought high. A new CS falling edge is required

to re-initiate the serial communication.

Table 3-6. Address Key

Address AT25128A AT25256A

 A

Don’t Care Bits A

 A

3368J–SEEPR–06/07

AT25128A_256A

4. Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 4-1. Synchronous Data Timing

Figure 4-2. WREN Timing

HI-Z

VALID IN

DIS

SCK

CSH

CSS

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

AT25128AW-10SU-1.8

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