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AT25128AW-10SU-1.8

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AT25128A_256A
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of
CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128A/256A.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
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3368J–SEEPR–06/07
AT25128A_256A
Figure 2-1. SPI Serial Interface
AT25128A/256A
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3368J–SEEPR–06/07
AT25128A_256A
3. Functional Description
The AT25128A/256A is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their opera-
tion codes are contained in see Table 4-3. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low
CS transition.
WRITE ENABLE (WREN): The device will power-up in the write disable state when V
CC
is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The Ready/Busy and Write Enable status of the device can be determined by
the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Table 3-1. Instruction Set for the AT25128A/256A
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
Table 3-2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN
RDY
Table 3-3. Read Status Register Bit Definition
Bit Definition
Bit0(RDY)
Bit 0 = “0” (
RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit1=0indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
Bit 2 (BP0) See
Table 3-4 on page 10.
Bit 3 (BP1) See
Table 3-4 on page 10.
Bits 4 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See
Table 3-5 on page 10.
Bits 0 7 are “1”s during an internal write cycle.
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AT25128AW-10SU-1.8

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IC EEPROM 128K SPI 20MHZ 8SOIC
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