NDH8304P

May 1997
NDH8304P
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
___________________________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter
NDH8304P
Units
V
DSS
Drain-Source Voltage -20 V
V
GSS
Gate-Source Voltage ±8 V
I
D
Drain Current - Continuous (Note 1) -2.7 A
- Pulsed -10
P
D
Maximum Power Dissipation (Note 1) 0.8 W
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θJA
Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W
R
θJC
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
NDH8304P Rev.C
SuperSOT
TM
-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
-2.7 A, -20 V. R
DS(ON)
= 0.07 @ V
GS
= -4.5 V
R
DS(ON)
= 0.095 @ V
GS
= -2.7 V.
Proprietary SuperSOT
TM
-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
1
5
7
8
2
6
3
4
© 1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage V
GS
= 0 V, I
D
= -250 µA -20 V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-1 µA
T
J
= 55°C
-10 µA
I
GSSF
Gate - Body Leakage, Forward V
GS
= 8 V, V
DS
= 0 V 100 nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -8 V, V
DS
= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= - 250 µA -0.4 -0.7 -1 V
T
J
= 125°C
-0.3 -0.5 -0.8
R
DS(ON)
Static Drain-Source On-Resistance V
GS
= -4.5 V, I
D
= -2.7 A 0.061 0.07
T
J
= 125°C
0.087 0.125
V
GS
= -2.7 V, I
D
= -2.3 A
0.082 0.095
I
D(on)
On-State Drain Current
V
GS
= -4.5 V, V
DS
= -5 V
-10 A
V
GS
= -2.7 V, V
DS
= -5 V
-3
g
FS
Forward Transconductance
V
DS
= -5 V, I
D
= -2.7 A
8 S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
865 pF
C
oss
Output Capacitance 415 pF
C
rss
Reverse Transfer Capacitance 150 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -5 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
11 22 ns
t
r
Turn - On Rise Time 25 50 ns
t
D(off)
Turn - Off Delay Time 78 150 ns
t
f
Turn - Off Fall Time 55 100 ns
Q
g
Total Gate Charge
V
DS
= -10 V,
I
D
= -2.7 A, V
GS
= -4.5 V
16 23 nC
Q
gs
Gate-Source Charge 2.4 nC
Q
gd
Gate-Drain Charge 5.1 nC
NDH8304P Rev.C
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current -0.67 A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.67 A (Note 2)
-0.7 -1.2 V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
)
=
T
J
T
A
R
θJA
(t)
=
T
J
T
A
R
θ
JC
+R
θ
CA
(t)
= I
D
2
(t) ×R
DS(ON ) T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
156
o
C/W when mounted on a 0.0025 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDH8304P Rev.C

NDH8304P

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET Dual P-Ch FET Enhancement Mode
Lifecycle:
New from this manufacturer.
Delivery:
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