10
LTC34 08
3408f
I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate
charges of the internal top and bottom switches. Both the
DC bias and gate charge losses are proportional to V
IN
,
thus, their effects will be more pronounced at higher
supply voltages. (The gate charge of the bypass FET is,
of course, negligible because it is infrequently cycled.)
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Charateristics
curves. Hence, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3408 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3408 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To prevent the LTC3408 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (PD)(θ
JA
)
where PD is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3408 in dropout at an
input voltage of 2.7V, a load current of 600mA (0.9V ≤ V
REF
< 1.2V) and an ambient temperature of 70°C. With V
REF
<
1.2V, the entire 600mA flows through the main P-channel
FET. From the typical performance graph of switch resis-
tance, the R
DS(ON)
of the P-channel switch at 70°C is
approximately 0.52Ω. Therefore, power dissipated by the
part is:
PD = (I
LOAD
2
) • R
DS(ON)
= 187.2mW
For the 8L DFN package, the θ
JA
is 43°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.1872)(43) = 78°C
which is below the maximum junction temperature of
125°C.
Modifying this example, suppose that V
REF
is raised to
1.2V or higher. This turns on the bypass P-channel FET as
well as the main P-channel FET. Assume that the inductor’s
DC resistance is 0.1Ω, the R
DS(ON)
of the main P-channel
switch is 0.52Ω, and the R
DS(ON)
of the bypass P-channel
switch is 0.08Ω. The current through the P-channel switch
and the inductor will be 69mA, causing power dissipation
of (0.069A)
2
• 0.62Ω = 2.9mW. The bypass FET will
APPLICATIO S I FOR ATIO
WUUU
Figure 4. Power Lost vs Load Current
LOAD CURRENT (mA)
1
0.01
POWER LOST (W)
EFFICIENCY (%)
0.01
0.1
1
0
20
10
60
30
70
40
80
50
90
100
10 100 1000
3408 F04
V
OUT
= 1.2V
V
OUT
= 1.5V
V
OUT
= 1.8V
V
OUT
= 2.5V
