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CBTU4411 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 18 June 2012 7 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance
Table 4. Function selection, channel 10
H = HIGH voltage level; L = LOW voltage level; high-Z = high-impedance; X = Don’t care.
Inputs Function
0DP10 1DP10 2DP10 3DP10
EN S1 S0 STREN HP10 VBIAS V
DD
HP10 VBIAS V
DD
HP10 VBIAS V
DD
HP10 VBIAS V
DD
LLL L R
ON
high-Z high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z
LLL H R
ON
high-Z high-Z high-Z R
pd
R
PU
high-Z R
pd
R
PU
high-Z R
pd
R
PU
LLH Lhigh-ZR
pd
high-Z R
ON
high-Z high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z
LLH Hhigh-ZR
pd
R
PU
R
ON
high-Z high-Z high-Z R
pd
R
PU
high-Z R
pd
R
PU
LHL Lhigh-ZR
pd
high-Z high-Z R
pd
high-Z R
ON
high-Z high-Z high-Z R
pd
high-Z
LHL Hhigh-ZR
pd
R
PU
high-Z R
pd
R
PU
R
ON
high-Z high-Z high-Z R
pd
R
PU
LHH Lhigh-ZR
pd
high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z R
ON
high-Z high-Z
LHH Hhigh-ZR
pd
R
PU
high-Z R
pd
R
PU
high-Z R
pd
R
PU
R
ON
high-Z high-Z
HXX Lhigh-ZR
pd
high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z high-Z R
pd
high-Z
H X X H high-Z high-Z R
PU
high-Z high-Z R
PU
high-Z high-Z R
PU
high-Z high-Z R
PU
Table 5. S0, S1 input termination
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
EN TERM Sn input termination
L L Termination resistors on S0, S1 inputs disconnected (high-impedance).
L H Termination resistors on S0, S1 inputs active.
H X Pull-down to GND via R
T
× 2. Also disables the S0, S1 input receivers for power savings.
CBTU4411 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 18 June 2012 8 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance
7. Limiting values
[1] The input and output negative voltage ratings may be exceeded if the input and output clamping current
ratings are observed.
8. Recommended operating conditions
[1] V
bias
>0.5× V
DD
is reserved for test purposes only.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
The package thermal impedance is calculated in accordance with JESD 51.
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +2.5 V
I
IK
input clamping current V
I/O
<0V - 50 mA
V
I
input voltage S0, S1 pins only
[1]
-V
DD
+0.3 V
except S0, S1 pins
[1]
0.5 +2.5 V
T
stg
storage temperature 65 +150 °C
Table 7. Operating conditions
All unused control inputs of the device must be held at V
DD
or GND to ensure proper device operation.
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 1.7 - 1.9 V
V
ref
reference voltage 0.49 × V
DD
0.50 × V
DD
0.51 × V
DD
V
V
bias
bias voltage pull-down resistor input
[1]
00.30× V
DD
0.33 × V
DD
V
V
T
termination voltage V
ref
0.04 V
ref
V
ref
+0.04 V
V
i
input voltage 0 - V
DD
V
V
IH(AC)
AC HIGH-level input voltage S0, S1 inputs V
ref
+0.250--V
V
IL(AC)
AC LOW-level input voltage S0, S1 inputs - - V
ref
0.250 V
V
IH(DC)
DC HIGH-level input voltage S0, S1 inputs V
ref
+0.125--V
V
IL(DC)
DC LOW-level input voltage S0, S1 inputs - - V
ref
0.125 V
V
IH
HIGH-level input voltage EN, STREN, TERM pins 0.65 × V
DD
--V
V
IL
LOW-level input voltage EN, STREN, TERM pins - - 0.35 × V
DD
V
T
amb
ambient temperature operating in free air 0 - +85 °C
CBTU4411 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 18 June 2012 9 of 21
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance
9. Static characteristics
[1] All typical values are at V
DD
= 1.8 V, T
amb
=25°C.
[2] Measured by the current between the host and the DIMM terminals at the indicated voltages on each side of the switch.
Table 8. Static characteristics
T
amb
=0
°
C to +85
°
C
Symbol Parameter Conditions Min Typ
[1]
Max Unit
V
IK
input clamping voltage V
DD
=1.7V; I
I
= 18 mA - - 1.2 V
V
T
termination voltage on S0, S1 inputs when
Sn = open circuit and
TERM = HIGH
0.5V
DD
0.04 0.5V
DD
0.5V
DD
+0.04 V
V
pu
pull-up voltage channel 10 DIMM port;
EN =LOW; V
bias
= 0.54 V;
V
DD
= 1.8 V; STREN = HIGH;
unselected DIMM port
0.5V
DD
+ 0.25 0.75V
DD
0.75V
DD
+0.25 V
I
LI
input leakage current V
DD
=1.8V; V
I
=V
DD
or GND;
Sn = V
DD
; V
bias
=V
DD
;
TERM = LOW
S0, S1 - - ±100 μA
host port - - ±100 μA
DIMM port - - ±100 μA
I
DD
supply current V
DD
=1.8V; I
O
=0A;
V
I
=V
DD
or GND
EN
=LOW - 6 9 mA
EN
=HIGH - 5 100 μA
C
in
input capacitance S0, S1 pins; V
I
=1.8V or 0V - 3 - pF
C
sw
switch capacitance switch ON; V
I
=0.9V - 4 6 pF
R
ON
ON resistance V
DD
=1.8V; V
HPn
=V
ref
;
V
xDPn
=V
ref
± 250 mV
[2]
10 12 17 Ω
V
DD
=1.8V; V
HPn
=V
ref
;
V
xDPn
=V
ref
± 500 mV
[2]
10 12 17 Ω
R
pd
pull-down resistance EN = HIGH; V
bias
= 0.54 V;
V
DD
=1.8V
280 400 520 Ω
channel 10; STREN = LOW 280 400 520 Ω
channel 10; STREN = HIGH 780 1120 1460 Ω
R
PU
pull-up resistance EN = HIGH; V
bias
= 0.54 V;
V
DD
=1.8V;
channel 10; STREN = HIGH
430 622 810 Ω
R
T
termination resistance Sn input; Thevenin equivalent
(see Figure 1
); input voltage
sweep 0 < V
I
(Sn) < V
DD
;
TERM = HIGH
55 80 105 Ω

CBTU4411EE,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Multiplexer Switch ICs CBTU4411EE/LFBGA72///TRAY SINGLE DP BAKEABLE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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