AT90CAN128-16MU Datasheet AT90CAN128-16MU, AT90CAN64-16MU, AT90CAN128-16AU | P7-P9

7679HS–CAN–08/08

AT90CAN32/64/128

1.6.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 74.

1.6.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 76.

1.6.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page

78.

1.6.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 80.

1.6.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 83.

1.6.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

7679HS–CAN–08/08

AT90CAN32/64/128

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-

up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

1.6.9 Port G (PG4..PG0)

Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output

buffers have symmetrical drive characteristics with both high sink and source capability. As

inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are

activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 88.

1.6.10 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed

to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if

the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.

1.6.11 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

1.6.12 XTAL2

Output from the inverting Oscillator amplifier.

1.6.13 AVCC

AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-

nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

1.6.14 AREF

This is the analog reference pin for the A/D Converter.

2. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

7679HS–CAN–08/08

AT90CAN32/64/128

3. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved

(0xFE) Reserved

(0xFD) Reserved

(0xFC) Reserved

(0xFB) Reserved

(0xFA) CANMSG MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 page 266

(0xF9) CANSTMH TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 page 266

(0xF8) CANSTML TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 page 266

(0xF7) CANIDM1

IDMSK

21 page 265

(0xF6) CANIDM2

IDMSK

13 page 265

(0xF5) CANIDM3

IDMSK

5 page 265

(0xF4) CANIDM4

IDMSK

0RTRMSK –IDEMSK page 265

(0xF3) CANIDT1

IDT

21 page 263

(0xF2) CANIDT2

IDT

13 page 263

(0xF1) CANIDT3

IDT

5 page 263

(0xF0) CANIDT4

IDT

0 RTRTAG RB1TAG RB0TAG page 263

(0xEF) CANCDMOB CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 page 262

(0xEE) CANSTMOB DLCW TXOK RXOK BERR SERR CERR FERR AERR page 261

(0xED) CANPAGE MOBNB3 MOBNB2 MOBNB1 MOBNB0 AINC INDX2 INDX1 INDX0 page 260

(0xEC) CANHPMOB HPMOB3 HPMOB2 HPMOB1 HPMOB0 CGP3 CGP2 CGP1 CGP0 page 260

(0xEB) CANREC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 page 260

(0xEA) CANTEC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 page 260

(0xE9) CANTTCH TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 page 260

(0xE8) CANTTCL TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 page 260

(0xE7) CANTIMH CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 page 259

(0xE6) CANTIML CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 page 259

(0xE5) CANTCON TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSC0 page 259

(0xE4) CANBT3

– PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP page 258

(0xE3) CANBT2 – SJW1 SJW0 – PRS2 PRS1 PRS0 – page 258

(0xE2) CANBT1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 – page 257

(0xE1) CANSIT1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 page 257

(0xE0) CANSIT2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 page 257

(0xDF) CANIE1 – IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8 page 257

(0xDE) CANIE2 IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 page 257

(0xDD) CANEN1 – ENMOB14 ENMOB13 ENMOB12 ENMOB11 ENMOB10 ENMOB9 ENMOB8 page 256

(0xDC) CANEN2 ENMOB7 ENMOB6 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0 page 256

(0xDB) CANGIE ENIT ENBOFF ENRX ENTX ENERR ENBX ENERG ENOVRT page 255

(0xDA) CANGIT CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG page 254

(0xD9) CANGSTA –OVRG – TXBSY RXBSY ENFG BOFF ERRP page 253

(0xD8) CANGCON ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES page 252

(0xD7) Reserved

(0xD6) Reserved

(0xD5) Reserved

(0xD4) Reserved

(0xD3) Reserved

(0xD2) Reserved

(0xD1) Reserved

(0xD0) Reserved

(0xCF) Reserved

(0xCE) UDR1 UDR17 UDR16 UDR15 UDR14 UDR13 UDR12 UDR11 UDR10 page 195

(0xCD) UBRR1H

– – – – UBRR111 UBRR110 UBRR19 UBRR18 page 199

(0xCC) UBRR1L UBRR17 UBRR16 UBRR15 UBRR14 UBRR13 UBRR12 UBRR11 UBRR10 page 199

(0xCB) Reserved

(0xCA) UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 page 198

(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 page 197

(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 page 195

(0xC7) Reserved

(0xC6) UDR0 UDR07 UDR06 UDR05 UDR04 UDR03 UDR02 UDR01 UDR00 page 195

(0xC5) UBRR0H

– – – – UBRR011 UBRR010 UBRR09 UBRR08 page 199

(0xC4) UBRR0L UBRR07 UBRR06 UBRR05 UBRR04 UBRR03 UBRR02 UBRR01 UBRR00 page 199

(0xC3) Reserved

(0xC2) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 page 197

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 page 196

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 page 195

(0xBF) Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AT90CAN128-16MU

Mfr. #:

Buy AT90CAN128-16MU

Manufacturer:

Microchip Technology / Atmel

Description:

8-bit Microcontrollers - MCU AVRC11N AVR UC 128K FLASH

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AT90CAN128-16MU

AT90CAN128-16MU

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