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LTC3410ESC6-1.875#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
LTC3410-1.875
34101875f
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3410-1.875 circuits: V
IN
quiescent current
and I
2
R losses. The V
IN
quiescent current loss dominates
the efficiency loss at very low load currents whereas the
I
2
R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since the
actual power lost is of no consequence as illustrated in
Figure 2.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the
gate charges of the internal top and bottom
switches. Both the DC bias and gate charge
losses are proportional to V
IN
and thus their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
APPLICATIO S I FOR ATIO
WUUU
LOAD CURRENT (mA)
0.1 1
0.00001
POWER LOSS (W)
0.001
1
10 100 1000
34101875 F02
0.0001
0.01
0.1
V
IN
= 3.6V
Figure 2. Power Loss vs Load Current
11
LTC3410-1.875
34101875f
Thermal Considerations
In most applications the LTC3410-1.875 does not dissi-
pate much heat due to its high efficiency. But, in applica-
tions where the LTC3410-1.875 is running at high ambient
temperature with low supply voltage, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150°C, both power switches will be turned off and the SW
node will become high impedance.
To prevent the LTC3410-1.875 from exceeding the maxi-
mum junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3410-1.875 with an input
voltage of 2.7V, a load current of 300mA and an ambient
temperature of 70°C. From the typical performance
graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 1.05Ω and
the R
DS(ON)
of the N-channel synchronous switch is ap-
proximately 0.75Ω. The series resistance looking into the
SW pin is:
R
SW
= 1.05Ω (0.69) + 0.75Ω (0.31) = 0.96Ω
Therefore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 86.4mW
For the SC70 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.0864)(250) = 91.6°C
which is well below the maximum junction temperature
of 125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The dis-
charged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
APPLICATIO S I FOR ATIO
WUUU
12
LTC3410-1.875
34101875f
APPLICATIO S I FOR ATIO
WUUU
Figure 3. LTC3410-1.875 Layout Diagram
RUN
LTC3410-1.875
GND
SW
L1
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
34101875 F03
4
6
5
1
3
+
–
2
V
OUT
V
IN
C
IN
C
OUT
Figure 4. LTC3410-1.875 Suggested Layout
LTC3410-
1.875
34101875 F04
PIN 1
V
OUT
V
IN
SW
VIA TO V
IN
C
OUT
C
IN
L1
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3410-1.875. These items are also illustrated graphi-
cally in Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
3. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
Design Example
As a design example, assume the LTC3410-1.875 is used
in a single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. With this informa-
tion we can calculate L using Equation (1),
L
fI
V
V
V
L
OUT
OUT
IN
=
()
∆
()
−
⎛
⎝
⎜
⎞
⎠
⎟
1
13()
Substituting V
OUT
= 1.875V, V
IN
= 4.2V, ∆I
L
= 100mA
and f = 2.25MHz in Equation (3) gives:
L
V
MHz mA
V
V
= −
⎛
⎝
⎜
⎞
⎠
⎟
=
1 875
2 25 100
1
1 875
42
4
.
.()
.
.
.66µH
A 4.7µH inductor works well for this application. For best
efficiency choose a 360mA or greater inductor with less
than 0.3Ω series resistance.
C
IN
will require an RMS current rating of at least 0.125A ≅
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.5Ω. In most cases, a ceramic capacitor will
satisfy this requirement.
Figure 5 shows the complete circuit along with its
efficiency curve.
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LTC3410ESC6-1.875#TRPBF

Mfr. #:
Buy LTC3410ESC6-1.875#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.875V ,300mA, 2.25MHz Synch Step-Dwn in SC70
Lifecycle:
New from this manufacturer.
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