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LTC3548AIMSE#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC3548A
10
3548afa
APPLICATIONS INFORMATION
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PART NUMBER VALUE
MAX DC
CURRENT DCR HEIGHT
Taiyo
Yuden
CB2016T2R2M
CB2012T2R2M
CB2016T3R3M
2.2μH
2.2μH
3.3μH
510mA
530mA
410mA
0.13Ω
0.33Ω
0.27Ω
1.6mm
1.25mm
1.6mm
Panasonic ELT5KT4R7M 4.7μH 950mA 0.2Ω 1.2mm
Sumida CDRH2D18/LD 4.7μH 630mA 0.086Ω 2mm
Murata LQH32CN4R7M23 4.7μH 450mA 0.2Ω 2mm
Taiyo
Yuden
NR30102R2M
NR30104R7M
2.2μH
4.7μH
1100mA
750mA
0.1Ω
0.19Ω
1mm
1mm
FDK FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7μH
3.3μH
2.2μH
1100mA
1200mA
1300mA
0.11Ω
0.1Ω
0.08Ω
1mm
1mm
1mm
TDK VLF3010AT4R7-
MR70
VLF3010AT3R3-
MR87
VLF3010AT2R2-
M1R0
4.7μH
3.3μH
2.2μH
700mA
870mA
1000mA
0.28Ω
0.17Ω
0.12Ω
1mm
1mm
1mm
Input Capacitor (C
IN
) Selection
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V
OUT
/V
IN
.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
ΔV
OUT
≈ΔI
L
ESR +
1
8f
O
C
OUT
⎛
⎝
⎜
⎞
⎠
⎟
where the maximum average output current I
MAX
equals
the peak current minus half the peak-to-peak ripple cur-
rent, I
MAX
= I
LIM
– ΔI
L
/2.
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
V
IN
for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance
is adequate for filtering. The output ripple (ΔV
OUT
) is
determined by:
ΔV
OUT
≈ΔI
L
ESR +
1
8f
O
C
OUT
⎛
⎝
⎜
⎞
⎠
⎟
where f
O
= operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage. With ΔI
L
= 0.3 • I
LIM
the output ripple
will be less than 100mV at maximum V
IN
and f
O
= 2.25MHz
with:
ESR
COUT
< 150mΩ
Once the ESR requirements for C
OUT
have been met, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantulum capacitors are all available in surface mount
packages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR (size) product
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP, of-
fer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density. However, they also have a larger
ESR and it is critical that they are surge tested for use
in switching power supplies. An excellent choice is the
LTC3548A
11
3548afa
APPLICATIONS INFORMATION
AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors have a significantly larger ESR, and
are often used in extremely cost-sensitive applications
provided that consideration is given to ripple current rat-
ings and long term reliability. Ceramic capacitors have the
lowest ESR and cost, but also have the lowest capacitance
density, a high voltage and temperature coefficient, and
exhibit audible piezoelectric effects. In addition, the high
Q of ceramic capacitors along with trace inductance can
lead to significant ringing. Other capacitor types include
the Panasonic Special Polymer (SP) capacitors.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3548A in parallel with the
main capacitors for high frequency decoupling.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR generates
a loop zero at 5kHz to 50kHz that is instrumental in giving
acceptable loop-phase margin. Ceramic capacitors remain
capacitive to beyond 300kHz and usually resonate with
their ESL before ESR becomes effective. Also, ceramic
capacitors are prone to temperature effects which require
the designer to check loop stability over the operating
temperature range. To minimize their large temperature and
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V
IN
pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, 3-4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, V
DROOP
, is
usually about 3 times the linear drop of the first cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
C
OUT
≈3
ΔI
OUT
f
O
•V
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3548A develops a 0.6V reference voltage between
the feedback pin, V
FB
, and ground as shown in Figure 1.
The output voltage is set by a resistive divider according
to the following formula:
V
OUT
= 0.6V 1+
R2
R1
⎛
⎝
⎜
⎞
⎠
⎟
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feedforward capaci-
tor, C
F
, may also be used. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line.
LTC3548A
12
3548afa
APPLICATIONS INFORMATION
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 2
16
clock cycles (about 29ms
in pulse-skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can
be bypassed by tying the POR output to the MODE/SYNC
input, to force pulse-skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. This can be avoided by using pulse-skipping mode
instead. When either channel is shut down, the POR output
is pulled low, since one or both of the channels are not
in regulation.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V
IN
enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse-skipping operation is selected which
provides the lowest output ripple, at the cost of low cur-
rent efficiency.
The LTC3548A can also be synchronized to another
LTC3548A by the MODE/SYNC pin. During synchroniza-
tion, the mode is set to pulse-skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feedforward capacitor can be
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creating high frequency zeros with R2 and R4 respectively,
which improve the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
Soft-Start
The RUN/SS pins provide a means to separately run or
shut down the two regulators. In addition, they can option-
ally be used to externally control the rate at which each
regulator starts up and shuts down. Pulling the RUN/SS1
pin below 1V shuts down regulator 1 on the LTC3548A.
Forcing this pin to V
IN
enables regulator 1. In order to
control the rate at which each regulator turns on and off,
connect a resistor and capacitor to the RUN/SS pins as
shown in Figure 1. The soft-start duration can be calculated
by using the following formula:
t
SS
=R
SS
C
SS
In
V
IN
−1
V
IN
−1.6
⎛
⎝
⎜
⎞
⎠
⎟
(s)
Hot Swap is a registered trademark of Linear Technology Corporation.
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LTC3548AIMSE#TRPBF

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Buy LTC3548AIMSE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Synchronous 400mA/800mA, 2.25MHz Step-Down DC/DC Regulator
Lifecycle:
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