CY62128BLL-70ZRXET

CY62128B
MoBL
Document #: 38-05300 Rev. *C Page 4 of 11
\
Capacitance
[6]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
9pF
C
OUT
Output Capacitance 9 pF
AC Test Loads and Waveforms
Data Retention Characteristics (Over the Operating Range for “LL” version only)
Parameter Description Conditions Min. Typ. Max. Unit
V
DR
V
CC
for Data Retention 2.0 V
I
CCDR
Data Retention Current V
CC
= V
DR
= 2.0V, CE
1
V
CC
– 0.3V,
or CE
2
0.3V, V
IN
V
CC
– 0.3V or, V
IN
0.3V
1.5 15 µA
t
CDR
Chip Deselect to Data Retention
Time
0ns
t
R
Operation Recovery Time 70 ns
90%
10%
V
CC
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R1 1800
R1 1800
R2
990
R2
990
639
Equivalent to: THÉVENIN EQUIVALENT
1.77V
Rise TIme:
1 V/ns
Fall TIme
:
1 V/ns
Data Retention Waveform
V
CC
, min.
V
CC
, min.
t
CDR
V
DR
>
2 V
DATA RETENTION MODE
t
R
CE
1
V
CC
CE
2
or
CY62128B
MoBL
Document #: 38-05300 Rev. *C Page 5 of 11
Switching Characteristics
[7]
Over the Operating Range
Parameter Description
62128B-55 62128B-70
UnitMin. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 55 70 ns
t
AA
Address to Data Valid 55 70 ns
t
OHA
Data Hold from Address Change 5 5 ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid 55 70 ns
t
DOE
OE LOW to Data Valid 20 35 ns
t
LZOE
OE LOW to Low Z 0 0 ns
t
HZOE
OE HIGH to High Z
[8, 9]
20 25 ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[9]
55ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[8, 9]
20 25 ns
t
PU
CE
1
LOW to Power-up, CE
2
HIGH to Power-up 0 0 ns
t
PD
CE
1
HIGH to Power-down, CE
2
LOW to Power-down 55 70 ns
WRITE CYCLE
[10]
t
WC
Write Cycle Time 55 70 ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End 45 60 ns
t
AW
Address Set-up to Write End 45 60 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-up to Write Start 0 0 ns
t
PWE
WE Pulse Width 45 50 ns
t
SD
Data Set-up to Write End 25 30 ns
t
HD
Data Hold from Write End 0 0 ns
t
LZWE
WE HIGH to Low Z
[9]
55ns
t
HZWE
WE LOW to High Z
[8, 9]
20 25 ns
Switching Waveforms
Read Cycle No.1
[12, 13]
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
11. No input may exceed V
CC
+ 0.5V.
12. Device is continuously selected. OE
, CE
1
= V
IL
, CE
2
= V
IH
.
13. WE
is HIGH for read cycle.
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
CY62128B
MoBL
Document #: 38-05300 Rev. *C Page 6 of 11
Read Cycle No. 2 (OE Controlled)
[13, 14]
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[15, 16]
Notes:
14. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
15. Data I/O is high impedance if OE
= V
IH
.
16. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O

CY62128BLL-70ZRXET

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1M PARALLEL 32TSOP I
Lifecycle:
New from this manufacturer.
Delivery:
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