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ISL83204AIPZ

P1-P3P4-P6P7-P9P10-P12P13-P15
13
FN6397.2
March 20, 2007
FIGURE 28. PEAK PULLUP CURRENT I
O+
vs SUPPLY
VOLTAGE
FIGURE 29. LOW VOLTAGE BIAS CURRENT I
DD
AND I
CC
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
Typical Performance Curves V
DD
= V
CC
= V
AHB
= V
BHB
= 12V, V
SS
= V
ALS
= V
BLS
= V
AHS
= V
BHS
= 0V, R
HDEL
= R
LDEL
=
100K, and T
A
= +25°C, Unless Otherwise Specified. (Continued)
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
V
CC
, V
DD
, V
ABH
, V
BHB
(V)
1k 10k 100k 1M2k 5k 20k 50k 500k200k
0.1
1
10
100
500
50
5
0.5
200
20
2
0.2
LOW VOLTAGE BIAS CURRENT (mA)
SWITCHING FREQUENCY (Hz)
3,000
1,000
10,000
100
10k 100k 1M20k 50k 200k 500k
10
100
1000
20
50
200
500
LEVEL-SHIFT CURRENT (μA)
SWITCHING FREQUENCY (Hz)
8.2
8.4
8.6
8.8
9.0
50 25 0 25 50 75 100 125 150
UV+
UV-
TEMPERATURE (°C)
BIAS SUPPLY VOLTAGE, V
DD
(V)
10 50 100 150 200 250
0
30
60
90
120
150
HDEL/LDEL RESISTANCE (kΩ)
DEAD-TIME (ns)
ISL83204A
14
FN6397.2
March 20, 2007
ISL83204A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
e
A
0.300 BSC 7.62 BSC 6
e
B
- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N20 209
Rev. 0 12/93
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6397.2
March 20, 2007
ISL83204A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
M
B
S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) B
M
M
α
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.014 0.019 0.35 0.49 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N20 207
α
0° 8° 0° 8° -
Rev. 2 6/05
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL83204AIPZ

Mfr. #:
Buy ISL83204AIPZ
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 60-80 VDC HI FREQ H-BRDG DRVR W
Lifecycle:
New from this manufacturer.
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