Data Sheet ADuM2200/ADuM2201
Rev. G | Page 13 of 17
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM2200/ADuM2201 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins (see
Figure 12). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 3 for V
DD1
and between Pin 14 and Pin 16
for V
DD2
. The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and the
input power supply pin should not exceed 2 mm. Consider
bypassing between Pin 3 and Pin 7 and between Pin 9 and Pin 14
unless the ground pair on each package side is connected close
to the package.
GND
1
NC
V
DD1
V
IA
/V
OA
GND
2
NC
V
DD2
V
OA
/V
IA
V
IB
V
OB
NC
NC
GND
1
NC
NC
GND
2
07235-012
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device as
specified in Table 18, thereby leading to latch-up or permanent
damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to a logic high output.
INPUT (
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
07235-018
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM2200/ADuM2201 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM2200/
ADuM2201 components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 μs, the input side
is assumed to be unpowered or nonfunctional, and the isolator
output is forced to a default state by the watchdog timer circuit
(see Table 20 and Table 21).
The limitation on the magnetic field immunity of the ADuM2200/
ADuM2201 is set by the condition in which induced voltage in the
transformer receiving coil is large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3.3 V operating condition of
the ADuM2200/ADuM2201 is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ πr
n
2
; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
r
n
is the radius of the n
th
turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM2200/
ADuM2201 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder,
a maximum allowable magnetic field is calculated as shown
in Figure 14.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
07235-019
Figure 14. Maximum Allowable External Magnetic Flux Density
