AD7940BRJZ-REEL7 Datasheet AD7940BRMZ-REEL7, AD7940BRM-REEL7, AD7940BRJZ-REEL7 | P13-P15

AD7940

Rev. A | Page 12 of 20

ADC TRANSFER FUNCTION

The output coding of the AD7940 is straight binary. The

designed code transitions occur at successive integer LSB

values, i.e., 1 LSB, 2 LSBs. The LSB size is V

/16384. The ideal

transfer characteristic for the AD7940 is shown in Figure 14.

03305-0-007

000...000

111...111

1 LSB = V

/16384

1 LSB +V

–1 LSB

ANALOG INPUT

000...001

000...010

111...110

111...000

011...111

Figure 14. AD7940 Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 15 shows a typical connection diagram for the AD7940.

REF

is taken internally from V

and as such should be well

decoupled. This provides an analog input range of 0 V to V

The conversion result is output in a 16-bit word. This 16-bit

data stream consists of two leading zeros, followed by the 14

bits of conversion data, MSB first. For applications where power

consumption is a concern, the power-down mode should be

used between conversions or bursts of several conversions to

improve power performance (see the Modes of Operation

section).

In fact, because the supply current required by the AD7940 is so

low, a precision reference can be used as the supply source to

the AD7940. For example, a REF19x voltage reference (REF195

for 5 V or REF193 for 3 V) or an AD780 can be used to supply

the required voltage to the ADC (see Figure 15). This

configuration is especially useful if the power supply available is

quite noisy, or if the system supply voltages are at some value

other than the required operating voltage of the AD7940, e.g.,

15 V. The REF19x or AD780 will output a steady voltage to the

AD7940. Recommended decoupling capacitors are a 100 nF low

ESR ceramic (Farnell 335-1816) and a 10 µF low ESR tantalum

(Farnell 197-130).

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AD7940

0V TO V

INPUT

SCLK

SDATA

SERIAL

INTERFACE

µC/µP

GND

10µF

TANT

0.1µF

10µF

0.1µF

SUPPLY

REF193

Figure 15. Typical Connection Diagram

Digital Inputs

The digital inputs applied to the AD7940 are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied can go to 7 V and are not restricted by the

+ 0.3 V limit as on the analog inputs. For example, if the

AD7940 were operated with a V

of 3 V, 5 V logic levels could

be used on the digital inputs. However, it is important to note

that the data output on SDATA will still have 3 V logic levels

when V

= 3 V.

Another advantage of SCLK and

not being restricted by the

+ 0.3 V limit is the fact that power supply sequencing issues

are avoided. If one of these digital inputs is applied before V

there is no risk of latch-up as there would be on the analog

inputs if a signal greater than 0.3 V were applied prior to V

AD7940

Rev. A | Page 13 of 20

MODES OF OPERATION

The mode of operation of the AD7940 is selected by controlling

the (logic) state of the

signal during a conversion. There are

two possible modes of operation, normal and power-down. The

point at which

is pulled high after the conversion has been

initiated will determine whether or not the AD7940 will enter

power-down mode. Similarly, if already in power-down,

can

control whether the device will return to normal operation or

remain in power-down. These modes of operation are designed

to provide flexible power management options. These options

can optimize the power dissipation/throughput rate ratio for

differing application requirements.

NORMAL MODE

This mode provides the fastest throughput rate performance

because the user does not have to worry about the power-up

times with the AD7940 remaining fully powered all the time.

Figure 16 shows the general diagram of the operation of the

AD7940 in this mode.

The conversion is initiated on the falling edge of

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times,

must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

. If

is brought high any time after the 10th SCLK falling

edge, but before the 16th SCLK falling edge, the part will

remain powered up, but the conversion will be terminated and

SDATA will go back into three-state. At least 16 serial clock

cycles are required to complete the conversion and access the

complete conversion result.

may idle high until the next

conversion or may idle low until

returns high sometime

prior to the next conversion, effectively idling

low.

Once a data transfer is complete (SDATA has returned to three-

state), another conversion can be initiated after the quiet time,

QUIET

, has elapsed by bringing

low again.

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1 12 16

1 LEADING ZERO + CONVERSION RESULT

SCLK

SDATA

Figure 16. Normal Mode Operation

AD7940

Rev. A | Page 14 of 20

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate, and then the ADC is

powered down for a relatively long duration between these

bursts of several conversions. When the AD7940 is in power-

down, all analog circuitry is powered down.

To enter power-down, the conversion process must be

interrupted by bringing

high anywhere after the second

falling edge of SCLK and before the 10th falling edge of SCLK

as shown in Figure 17. Once

has been brought high in this

window of SCLKs, the part will enter power-down, the

conversion that was initiated by the falling edge of

will be

terminated, and SDATA will go back into three-state. If

brought high before the second SCLK falling edge, the part will

remain in normal mode and will not power down. This will

avoid accidental power-down due to glitches on the

line.

In order to exit this mode of operation and power up the

AD7940 again, a dummy conversion is performed. On the

falling edge of

, the device will begin to power up and will

continue to power up as long as

is held low until after the

falling edge of the 10th SCLK. The device will be fully powered

up once at least 16 SCLKs (or approximately 6 µs) have elapsed

and valid data will result from the next conversion as shown in

Figure 18. If

is brought high before the 10th falling edge of

SCLK, regardless of the SCLK frequency, the AD7940 will go

back into power-down again. This avoids accidental power-up

due to glitches on the

line or an inadvertent burst of 8 SCLK

cycles while

is low. So although the device may begin to

power-up on the falling edge of

, it will power down again on

the rising edge of

as long as it occurs before the 10th SCLK

falling edge.

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SCLK

SDATA

1 2 10 16

THREE-STATE

Figure 17. Entering Power-Down Mode

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1 10 16 1 16

SDATA

SCLK

INVALID DATA VALID DATA

THE PART IS FULLY POWERED

UP WITH V

FULLY ACQUIRED

THE PART BEGINS

TO POWER UP

POWER UP

Figure 18. Exiting Power-Down Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7940BRJZ-REEL7

Mfr. #:

Buy AD7940BRJZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3mW 100 kSPS 14-Bit

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AD7940BRJZ-REEL7

AD7940BRJZ-REEL7

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