OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7940BRJZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7940
Rev. A | Page 3 of 20
SPECIFICATIONS
1
V
DD
= 2.50 V to 5.5 V, f
SCLK
= 2.5 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter B Version
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)
2
81 dB min
Total Harmonic Distortion (THD)
2
−98 dB typ
Peak Harmonic or Spurious Noise (SFDR)
2
−95 dB typ
Intermodulation Distortion (IMD)
2
Second-Order Terms −94 dB typ
Third-Order Terms −100 dB typ
Aperture Delay 20 ns max
Aperture Jitter 30 ps typ
Full Power Bandwidth 7 MHz typ @ −3 dB
2 MHz typ @ −0.1 dB
DC ACCURACY
Resolution 14 Bits min V
DD
= 2.5 V to 4.096 V
13 Bits min V
DD
> 4.096 V
Integral Nonlinearity
2
±1 LSB max V
DD
= 2.5 V to 4.096 V
±2 LSB max V
DD
> 4.096 V
Offset Error
2
±6 LSB max
Gain Error
2
±8 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
V
DC Leakage Current ±0.3 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.4 V max V
DD
= 3 V
0.8 V max V
DD
= 5 V
Input Current, I
IN
±0.3 µA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
2, 3
10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
– 0.2 V min I
SOURCE
= 200 µA; V
DD
= 2.50 V to 5.25 V
Output Low Voltage, V
OL
0.4 V max I
SINK
= 200 µA
Floating-State Leakage Current ±0.3 µA max
Floating-State Output Capacitance
2, 3
10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 µs max 16 SCLK cycles
Track-and-Hold Acquisition Time 500 ns max Full-scale step input
400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 kSPS max See the Serial Interface section
POWER REQUIREMENTS
V
DD
2.50/5.5 V min/V max
I
DD
Digital I/P
S
= 0 V or V
DD
Normal Mode (Static) 5.2 mA max V
DD
= 5.5 V; SCLK on or off
2 mA max V
DD
= 3.6 V; SCLK on or off
Normal Mode (Operational) 4.8 mA max V
DD
= 5.5 V; f
SAMPLE
= 100 kSPS; 3.3 mA typ
1.9 mA max V
DD
= 3.6 V; f
SAMPLE
= 100 kSPS; 1.29 mA typ
Full Power-Down Mode 0.5 µA max SCLK on or off. V
DD
= 5.5 V
0.3 µA max SCLK on or off. V
DD
= 3.6 V
AD7940
Rev. A | Page 4 of 20
Parameter B Version
1
Unit Test Conditions/Comments
Power Dissipation
4
V
DD
= 5.5 V
Normal Mode (Operational) 26.4 mW max V
DD
= 5.5 V; f
SAMPLE
= 100 kSPS
6.84 mW max V
DD
= 3.6 V; f
SAMPLE
= 100 kSPS
Full Power-Down 2.5 µW max V
DD
= 5.5 V
1.08 µW max V
DD
= 3.6 V
1
Temperature range for B Version is –40°C to +85°C.
2
See the Terminology section.
3
Sample tested at initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.
AD7940
Rev. A | Page 5 of 20
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from
a voltage level of 1.6 V.
V
DD
= 2.50 V to 5.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN
, T
MAX
Parameter 3 V 5 V Unit Description
f
SCLK
1
250 250 kHz min
2.5 2.5 MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
min
t
QUIET
50 50 ns min Minimum quiet time required between bus relinquish and start of
next conversion
t
1
10 10 ns min
Minimum
CS
pulse width
t
2
10 10 ns min
CS
to SCLK setup time
t
3
2
48 35 ns max
Delay from
CS
until SDATA three-state disabled
t
4
2
120 80 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
0.4 t
ns min SCLK low pulse width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK high pulse width
t
7
10 10 ns min SCLK to data valid hold time
t
8
3
45 35 ns max SCLK falling edge to SDATA high impedance
t
POWER-UP
4
1 1 µs typ Power up time from full power-down
1
Mark/space ratio for the SCLK input is 40/60 to 60/40.
2
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4
See the Power vs. Throughput Rate section.
03305-0-002
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7940BRJZ-REEL7

Mfr. #:
Buy AD7940BRJZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3mW 100 kSPS 14-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet